CY7C68000A-56BAXC

CY7C68000A-56BAXC Datasheet


CY7C68000A

Part Datasheet
CY7C68000A-56BAXC CY7C68000A-56BAXC CY7C68000A-56BAXC (pdf)
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CY7C68000A-56LFXCT CY7C68000A-56LFXCT CY7C68000A-56LFXCT
CY7C68000A-56LFXC CY7C68000A-56LFXC CY7C68000A-56LFXC
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CY7C68000A

MoBL-USB TX2 USB UTMI Transceiver

MoBL-USB TX2 Features
• UTMI-Compliant and USB Certified for Device Operation
• Operates in Both USB High Speed HS , 480 Mbits/second,
and Full Speed FS , 12 Mbits/second
• Optimized for Seamless Interface with Monahans Appli-
cations Processors
• Tristate Mode Enables Sharing of UTMI Bus with other Devices
• Serial-to-Parallel and Parallel-to-Serial Conversions
• 8-bit Unidirectional, 8-bit Bidirectional, or 16-bit Bidirectional

External Data Interface
• Synchronous Field and EOP Detection on Receive Packets
• Synchronous Field and EOP Generation on Transmit Packets
• Data and Clock Recovery from the USB Serial Stream
• Bit Stuffing and Unstuffing Bit Stuff Error Detection
• Staging Register to Manage Data Rate Variation due to Bit

Stuffing and Unstuffing
• 16-bit 30 MHz and 8-bit 60 MHz Parallel Interface
• Ability to Switch between FS and HS Terminations and

Signaling
• Supports Detection of USB Reset, Suspend, and Resume
• Supports HS Identification and Detection as defined by the USB

Specification

Logic Block Diagram
• Supports Transmission of Resume Signaling
• 3.3V Operation
• Two Package Options 56-pin QFN and 56-pin VFBGA
• All Required Terminations, Including Kohm Pull Up on DPLUS, are Internal to Chip
• Supports USB Test Modes

This product is also optimized to seamlessly interface with Monahans -P & -L applications processors. It has been characterized by Intel and is recommended as the USB UTMI transceiver of choice for its Monahans processors. It is also capable of tristating the UTMI bus, while suspended, to enable the bus to be shared with other devices.

Two packages are defined for the families 56-pin QFN and 56-pin VFBGA.

The functional block diagram follows.

Tri_state
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CY7C68000A

Mobile Applications
• Smart Phones
• PDA Phones
• Gaming Phones
• MP3 players
• Portable Media Players PMP
• GPS Tracking Devices Consumer Applications
• Cameras
• Scanners
• DSL Modems
• Memory Card Readers

Non-Consumer Applications
• Networking
• Wireless LAN
• Home PNA

Functional Overview

The functionality of this chip is described in the following sections USB Signaling Speed The MoBL-USB TX2 operates at two of the rates defined in the USB Specification dated
• Full speed, with a signaling bit rate of 12 Mbps
• High speed, with a signaling bit rate of 480 Mbps The MoBL-USB TX2 does not support the LS signaling rate of Mbps. Transceiver Clock Frequency The MoBL-USB TX2 has an on-chip oscillator circuit that uses an external 24 MHz ±100 ppm crystal with the following characteristics
• Parallel resonant
• Fundamental mode
• 500 uW drive level
• 27 to 33 pF 5% tolerance load capacitors

An on-chip phase-locked loop PLL multiplies the 24 MHz oscillator up to 30 or 60 MHz, as required by the transceiver parallel data bus. The default UTMI interface clock CLK frequency is determined by the DataBus16_8 pin.

Buses

The two packages enable a 8- or 16-bit bidirectional data bus for data transfers to a controlling unit.

Suspend and Tristate Modes

When the MoBL-USB TX2 is not in use, the processor reduces power consumption by putting it into Suspend mode using the Suspend pin.

While in Suspend mode, Tristate mode may be enabled, which tristates all outputs and I/Os, enabling the UTMI interface pins to be shared with other devices. This is valuable in mobile handset applications, where GPIOs are at a premium. The outputs and I/Os are tristated ~50ns when Tristate mode is enabled, and are driven ~50ns when Tri-state mode is disabled. All inputs must not be left floating while in Tristate mode.

When resuming after a suspend, the PLL stabilizes approximately 200 us after the suspend pin goes high.

Reset Pin

An input pin Reset resets the chip. This pin has hysteresis and is active HIGH according to the UTMI specification. The internal PLL stabilizes approximately 200 us after VCC has reached 3.3V.

Line State

The Line State output pins LineState[1:0] are driven by combinational logic and may be toggling between the ‘J’ and the ‘K’ states. They are synchronized to the CLK signal for a valid signal. On the CLK edge, the state of these lines reflect the state of the USB data lines. Upon the clock edge the ‘0’ bit of the LineState pins is the state of the DPLUS line and the ‘1’ bit of LineState is the DMINUS line. When synchronized, the setup and hold timing of the LineState is identical to the parallel data bus.

Full Speed versus High Speed Select

The FS versus HS is done through the use of both XcvrSelect and the TermSelect input signals. The TermSelect signal enables the Kohm pull up on to the DPLUS pin. When TermSelect is driven LOW, a SE0 is asserted on the USB providing the HS termination and generating the HS Idle state on the bus. The XcvrSelect signal is the control that selects either the FS transceivers or the HS transceivers. By setting this pin to a ‘0’ the HS transceivers are selected and by setting this bit to a’1’ the FS transceivers are selected.

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Ordering Information
Ordering Code CY7C68000A-56LFXC CY7C68000A-56BAXC CY7C68000A-56LTXC CY7C68000A-56LTXCT CY3683

Package Type 56 QFN 56 VFBGA 56 QFN 56 QFN MoBL-USB TX2 Development Board

Package Diagrams

The MoBL-USB TX2 is available in two packages:
• 56-pin QFN
• 56-pin VFBGA

Figure 56-Pin Quad Flatpack No Lead Package 8 x 8 mm Sawn Version
51-85187 *C

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CY7C68000A

Package Diagrams continued

Figure 56 VFBGA 5 x 5 x mm Pitch, Ball BZ56

TOP VIEW

PIN A1 CORNER
12 3 4 5 6 8 A B C D E F G H

SIDE VIEW

BOTTOM VIEW
-B-A0.10 4X

M C M C A B Ø0.30±0.05 56X

A1 CORNER
87654321

A B C D E F G H
-C- SEATING PLANE

REFERENCE JEDEC MO-195C PACKAGE WEIGHT grams
001-03901-*B

PCB Layout Recommendations

Follow these recommendations to ensure reliable, high performance operation[3].
• A four-layer impedance controlled board is required to maintain signal quality
• Specify impedance targets ask your board vendor what they can achieve
• To control impedance, maintain trace widths and trace spacing to within written specifications
• Minimize stubs to minimize reflected signals
• Connections between the USB connector shell and signal ground must be done near the USB connector
• Bypass and flyback capacitors on VBus, near the connector, are recommended
• Keep DPLUS and DMINUS trace lengths within 2 mm of each other in length, with preferred length of 20 to 30 mm
• Maintain a solid ground plane under the DPLUS and DMINUS traces. Do not split the plane under these traces
• Do not place vias on the DPLUS or DMINUS trace routing
• Isolate the DPLUS and DMINUS traces from all other signal traces by no less than 10 mm

Note

Source for recommendations EZ-USB FX2 PCB Design Recommendations, High-Speed USB Platform Design Guidelines,

Page 13 of 15
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05/22/2009 Updated Ordering Information for CY7C68000A-56LTXC and CY7C68000A-56LTXCT parts

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

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Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

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MoBL-USB TX2 is a trademark of Cypress Semiconductor Corporation. Intel is a registered trademark of Intel Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. All products and company names mentioned in this document may be the trademarks of their respective holders.
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Datasheet ID: CY7C68000A-56BAXC 508138