FDV302P-NB8V001

FDV302P-NB8V001 Datasheet

FDV302P Digital FET, P-Channel

Part	Datasheet
FDV302P-NB8V001	FDV302P-NB8V001 (pdf)

Related Parts	Information
FDV302P	FDV302P
FDV302P_D87Z	FDV302P_D87Z

PDF Datasheet Preview
October 1997 FDV302P Digital FET, P-Channel This P-Channel logic level enhancement mode field effect transistor is produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for digital transistors. Since bias resistors are not required, this one P-channel FET can replace several digital transistors with different bias resistors such as the DTCx and DCDx series. SOT-23 Mark:302 SuperSOTTM-6 SuperSOTTM-8 -25 V, A continuous, A Peak. RDS ON = 13 VGS= V RDS ON = 10 VGS = V. Very low level gate drive requirements allowing direct operation in 3V circuits. VGS th < 1.5V. Gate-Source Zener for ESD ruggedness. >6kV Human Body Model Compact industry standard SOT-23 surface mount package. Replace many PNP digital transistors DTCx and DCDx with one DMOS FET. SO-8 SOT-223 SOIC-16 Absolute Maximum Ratings TA = 25oC unless otherwise noted Symbol Parameter VDSS Drain-Source Voltage VGSS Gate-Source Voltage Drain Current - Continuous - Pulsed PD TJ,TSTG ESD Maximum Power Dissipation Operating and Storage Temperature Range Electrostatic Discharge Rating MIL-STD-883D Human Body Model 100pf / 1500 Ohm THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient 1997 Fairchild Semiconductor Corporation FDV302P -25 -8 -55 to 150 Units V A W °C kV °C/W Electrical Characteristics TA = 25 OC unless otherwise noted Symbol Parameter Conditions OFF CHARACTERISTICS BVDSS

PDF Datasheet Preview

October 1997

FDV302P Digital FET, P-Channel

This P-Channel logic level enhancement mode field effect transistor is produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for digital transistors. Since bias resistors are not required, this one P-channel FET can replace several digital transistors with different bias resistors such as the DTCx and DCDx series.

SOT-23 Mark:302

SuperSOTTM-6

SuperSOTTM-8
-25 V, A continuous, A Peak.

RDS ON = 13 VGS= V RDS ON = 10 VGS = V.

Very low level gate drive requirements allowing direct operation in 3V circuits. VGS th < 1.5V.

Gate-Source Zener for ESD ruggedness. >6kV Human Body Model

Compact industry standard SOT-23 surface mount package.

Replace many PNP digital transistors DTCx and DCDx with one DMOS FET.

SO-8

SOT-223

SOIC-16

Absolute Maximum Ratings TA = 25oC unless otherwise noted

Symbol Parameter

VDSS

Drain-Source Voltage

VGSS

Gate-Source Voltage

Drain Current
- Continuous
- Pulsed

PD TJ,TSTG ESD

Maximum Power Dissipation

Operating and Storage Temperature Range

Electrostatic Discharge Rating MIL-STD-883D Human Body Model 100pf / 1500 Ohm

THERMAL CHARACTERISTICS

Thermal Resistance, Junction-to-Ambient
1997 Fairchild Semiconductor Corporation

FDV302P -25 -8
-55 to 150

Units V A

W °C kV
°C/W

Electrical Characteristics TA = 25 OC unless otherwise noted

Symbol Parameter

Conditions

OFF CHARACTERISTICS

BVDSS

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived FDV302P-NB8V001 Datasheet file may be downloaded here without warranties.

Datasheet ID: FDV302P-NB8V001 514398