CY7C4255-10AXC

CY7C4255-10AXC Datasheet

CY7C4255, CY7C4265, CY7C4265A

Part	Datasheet
CY7C4255-10AXC	CY7C4255-10AXC (pdf)

Related Parts	Information
CY7C4255-10AC	CY7C4255-10AC
CY7C4255-15AXC	CY7C4255-15AXC
CY7C4255-10AXCT	CY7C4255-10AXCT

PDF Datasheet Preview
CY7C4255, CY7C4265, CY7C4265A 8K/16K x 18 Deep Sync FIFOs Functional Description • High Speed, Low Power, First-In First-Out FIFO Memories 8K x 18 CY7C4255 16K x 18 CY7C4265/4265A [1] • Micron CMOS for Optimum Speed and Power • High Speed 100 MHz Operation 10 ns read/write cycle times • Low Power ICC = 45 mA • Fully Asynchronous and Simultaneous Read and Write Operation • Empty, Full, Half Full, and Programmable Almost Empty and Almost Full Status Flags • TTL compatible • Retransmit Function • Output Enable OE Pins • Independent Read and Write Enable Pins • Center Power and Ground Pins for Reduced Noise • Supports Free-running 50 percent Duty Cycle Clock Inputs • Width and Depth Expansion Capability • 64-pin TQFP and 64-pin STQFP • Pin-compatible Density Upgrade to CY7C42X5 Family • Pin-compatible Density Upgrade to IDT72205/15/25/35/45 • Pb-free Packages Available Logic Block Diagram The CY7C4255/65/65A are high speed, low power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to the CY7C42X5 Synchronous FIFO family. The CY7C4255/65/65A can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free running Clock WCLK and a Write Enable pin WEN . When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled in a similar manner by a free-running Read Clock RCLK and a Read Enable pin REN . In addition, the CY7C4255/65/65A have an Output Enable pin OE . The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable. Retransmit and Synchronous Almost Full/Almost Empty flag features are available on these devices. Depth expansion is possible using the Cascade Input WXI, RXI , Cascade Output WXO, RXO , and First Load FL pins. The WXO and RXO pins are connected to the WXI and RXI pins of the next device, and the WXO and RXO pins of the last device should be connected to the WXI and RXI pins of the first device. The FL pin of the first device is tied to VSS and the FL pin of all the remaining devices should be tied to VCC. INPUT REGISTER WCLK WRITE CONTROL WRITE POINTER RESET LOGIC FL/RT WXI WXO/HF RXI RXO EXPANSION LOGIC Note CY7C4265 and CY7C4265A are functionally identical RAM ARRAY 8K x 18 16K x 18 FLAG PROGRAM REGISTER FLAG LOGIC READ POINTER FF EF PAF SMODE OUTPUT REGISTER READ CONTROL RCLK • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Ordering Information 8Kx18 Deep Sync FIFO Speed ns Ordering Code 16Kx18 Deep Sync FIFO Speed ns Ordering Code CY7C4265-15ASC Package Name 51-85046 51-85046 51-85051 51-85046 51-85046 Package Type 64-Pin Thin Quad Flatpack 64-Pin Thin Quad Flatpack Pb-free 64-Pin Small Thin Quad Flatpack 64-Pin Thin Quad Flatpack 64-Pin Thin Quad Flatpack Pb-free Operating Range Commercial Commercial Package Diagram 51-85046 51-85051 51-85051 51-85046 51-85046 51-85046 51-85046 51-85051 51-85051 Package Type 64-Pin Thin Quad Flatpack 64-Pin Small Thin Quad Flatpack 64-Pin Small Thin Quad Flatpack Pb-free 64-Pin Thin Quad Flatpack 64-Pin Thin Quad Flatpack Pb-free 64-Pin Thin Quad Flatpack 64-Pin Thin Quad Flatpack Pb-free 64-Pin Small Thin Quad Flatpack 64-Pin Small Thin Quad Flatpack Operating Range Commercial Industrial Commercial Industrial Page 20 of 23 [+] Feedback CY7C4255, CY7C4265, CY7C4265A Package Diagrams Figure 64-Pin Thin Plastic Quad Flat Pack 10 x 10 x mm , 51-85051 51-85051 A Page 21 of 23 [+] Feedback CY7C4255, CY7C4265, CY7C4265A Package Diagrams continued Figure 64-Pin Thin Plastic Quad Flat Pack 14 x 14 x mm , 51-85046 51-85046-B 51-85046-*B Page 22 of 23 [+] Feedback CY7C4255, CY7C4265, CY7C4265A Document History Page Document Title CY7C4255, CY7C4265, CY7C4265A 8K/16K X 18 Deep Sync FIFOs Document Number 38-06004 ECN NO. Orig. of Change Submission Date Description of Change 106465 07/11/01 Change from Spec Number 38-00468 to 38-06004 122257 12/26/02 Power up requirements added to Maximum Ratings Information 252889 See ECN Removed PLCC package and pruned parts from Order Information 385985 CY7C4255-10AXC, CY7C4255-15AXC to ordering information 2623658 VKN/PYRS 12/17/08 Added CY7C4265A part Updated Ordering information table 2714768 VKN/AESA 06/04/2009 Corrected defective Logic Block diagram, Pinouts, and Package diagrams Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 23 of 23 [+] Feedback

PDF Datasheet Preview

CY7C4255, CY7C4265, CY7C4265A
8K/16K x 18 Deep Sync FIFOs

Functional Description
• High Speed, Low Power, First-In First-Out FIFO Memories 8K x 18 CY7C4255 16K x 18 CY7C4265/4265A [1]
• Micron CMOS for Optimum Speed and Power
• High Speed 100 MHz Operation 10 ns read/write cycle times
• Low Power ICC = 45 mA
• Fully Asynchronous and Simultaneous Read and Write

Operation
• Empty, Full, Half Full, and Programmable Almost Empty and

Almost Full Status Flags
• TTL compatible
• Retransmit Function
• Output Enable OE Pins
• Independent Read and Write Enable Pins
• Center Power and Ground Pins for Reduced Noise
• Supports Free-running 50 percent Duty Cycle Clock Inputs
• Width and Depth Expansion Capability
• 64-pin TQFP and 64-pin STQFP
• Pin-compatible Density Upgrade to CY7C42X5 Family
• Pin-compatible Density Upgrade to IDT72205/15/25/35/45
• Pb-free Packages Available

Logic Block Diagram

The CY7C4255/65/65A are high speed, low power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to the CY7C42X5 Synchronous FIFO family. The CY7C4255/65/65A can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high speed data acquisition, multiprocessor interfaces, and communications buffering.

These FIFOs have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free running Clock WCLK and a Write Enable pin WEN . When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled in a similar manner by a free-running Read Clock RCLK and a Read Enable pin REN . In addition, the CY7C4255/65/65A have an Output Enable pin OE . The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable.

Retransmit and Synchronous Almost Full/Almost Empty flag features are available on these devices. Depth expansion is possible using the Cascade Input WXI, RXI , Cascade Output WXO, RXO , and First Load FL pins. The WXO and RXO pins are connected to the WXI and RXI pins of the next device, and the WXO and RXO pins of the last device should be connected to the WXI and RXI pins of the first device. The FL pin of the first device is tied to VSS and the FL pin of all the remaining devices should be tied to VCC.

INPUT REGISTER

WCLK

WRITE CONTROL

WRITE POINTER

RESET

LOGIC

FL/RT

WXI WXO/HF

RXI RXO

EXPANSION LOGIC

Note CY7C4265 and CY7C4265A are functionally identical

RAM ARRAY 8K x 18 16K x 18

FLAG PROGRAM REGISTER

FLAG LOGIC

READ POINTER

FF EF

PAF SMODE

OUTPUT REGISTER

READ CONTROL

RCLK
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback
Ordering Information
8Kx18 Deep Sync FIFO

Speed ns
Ordering Code
16Kx18 Deep Sync FIFO

Speed ns
Ordering Code

CY7C4265-15ASC

Package Name
51-85046 51-85046 51-85051 51-85046 51-85046

Package Type
64-Pin Thin Quad Flatpack 64-Pin Thin Quad Flatpack Pb-free 64-Pin Small Thin Quad Flatpack 64-Pin Thin Quad Flatpack 64-Pin Thin Quad Flatpack Pb-free

Operating Range

Commercial

Commercial

Package Diagram 51-85046 51-85051 51-85051 51-85046 51-85046 51-85046 51-85046 51-85051 51-85051

Package Type
64-Pin Thin Quad Flatpack 64-Pin Small Thin Quad Flatpack 64-Pin Small Thin Quad Flatpack Pb-free 64-Pin Thin Quad Flatpack 64-Pin Thin Quad Flatpack Pb-free 64-Pin Thin Quad Flatpack 64-Pin Thin Quad Flatpack Pb-free 64-Pin Small Thin Quad Flatpack 64-Pin Small Thin Quad Flatpack

Operating Range

Commercial

Industrial Commercial

Industrial

Page 20 of 23 [+] Feedback

CY7C4255, CY7C4265, CY7C4265A

Package Diagrams

Figure 64-Pin Thin Plastic Quad Flat Pack 10 x 10 x mm , 51-85051
51-85051 *A

Page 21 of 23 [+] Feedback

CY7C4255, CY7C4265, CY7C4265A

Package Diagrams continued

Figure 64-Pin Thin Plastic Quad Flat Pack 14 x 14 x mm , 51-85046
51-85046-*B 51-85046-*B

Page 22 of 23 [+] Feedback

CY7C4255, CY7C4265, CY7C4265A

Document History Page

Document Title CY7C4255, CY7C4265, CY7C4265A 8K/16K X 18 Deep Sync FIFOs Document Number 38-06004

ECN NO.

Orig. of Change

Submission Date

Description of Change
106465
07/11/01 Change from Spec Number 38-00468 to 38-06004
122257
12/26/02 Power up requirements added to Maximum Ratings Information
252889

See ECN Removed PLCC package and pruned parts from Order Information
385985
CY7C4255-10AXC, CY7C4255-15AXC to ordering information
2623658 VKN/PYRS 12/17/08 Added CY7C4265A part
Updated Ordering information table
2714768 VKN/AESA 06/04/2009 Corrected defective Logic Block diagram, Pinouts, and Package diagrams

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products PSoC Clocks & Buffers Wireless Memories Image Sensors
psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

All products and company names mentioned in this document may be the trademarks of their respective holders.

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More datasheets: AMG-300 | AMG-175 | AMG-225 | AMG-200 | 20039 | GPF13.3W | BC318C | 74ACT2708PC | 76000827 | CY7C4255-10AC

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Datasheet ID: CY7C4255-10AXC 508100