74ACT2708PC

74ACT2708PC Datasheet

74ACT2708 64 x 9 First-In, First-Out Memory

Part	Datasheet
74ACT2708PC	74ACT2708PC (pdf)

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74ACT2708 64 x 9 First-In, First-Out Memory 74ACT2708 64 x 9 First-In, First-Out Memory The ACT2708 is an expandable first-in, first-out memory organized as 64 words by 9 bits. An 85 MHz shift-in and 60 MHz shift-out typical data rate makes it ideal for high-speed applications. It uses a dual port RAM architecture with pointer logic to achieve the high speed with negligible fallthrough time. Separate Shift-In SI and Shift-Out SO clocks control the use of synchronous or asynchronous write or read. Other controls include a Master Reset MR and Output Enable OE for initializing the internal registers and allowing the data outputs to be 3-STATE. Input Ready IR and Output Ready OR signal when the FIFO is ready for I/O operations. The status flags HF and FULL indicate when the FIFO is full, empty or half full. The FIFO can be expanded to provide different word lengths by tying off unused data inputs. s 64-words by 9-bit dual port RAM organization s 85 MHz shift-in, 60 MHz shift-out data rate, typical s Expandable in word width only s TTL-compatible inputs s Asynchronous or synchronous operation s Asynchronous master reset s Outputs source/sink 8 mA s 3-STATE outputs s Full ESD protection s Input and output pins directly in line for easy board lay- out s TRW 1030 work-alike operation • High-speed disk or tape controllers • A/D output buffers • High-speed graphics pixel buffer • Video time base correction • Digital filtering Ordering Code: Order Number Package Number Package Description 74ACT2708PC N28B 28-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-010, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Assignment for DIP Pin Names MR OE SI SO IR OR HF FULL Description Data Inputs Master Reset Output Enable Input Shift-In Shift-Out Input Ready Output Ready Half Full Flag Full Flag Data Outputs FACT is a trademark of Fairchild Semiconductor Corporation. 1999 Fairchild Semiconductor Corporation DS010144.prf 74ACT2708 Logic Symbol Block Diagram 74ACT2708 Functional Description INPUTS Data Inputs Data inputs for 9-bit wide data are TTL-compatible. Word width can be reduced by trying unused inputs to ground and leaving the corresponding outputs open. Reset MR Reset is accomplished by pulsing the MR input LOW. During normal operation MR is HIGH. A reset is required after power up to guarantee correct operation. On reset, the data outputs go LOW, IR goes HIGH, OR goes LOW, FH and FULL go LOW. During reset, both internal read and write pointers are set to the first location in the array. Shift-In SI Data is written into the FIFO by pulsing SI HIGH. When Shift-In goes HIGH, the data is loaded into an internal data latch. Data setup and hold times need to be adhered to with respect to the falling edge of SI. The write cycle is complete after the falling edge of SI. The shift-in is independent of any ongoing shift-out operation. After the first word has been written into the FIFO, the falling edge of SI makes HF go HIGH, indicating a non-empty FIFO. The first data word appears at the output after the falling edge of SI. After half the memory is filled, the next rising edge of SI makes FULL go HIGH indicating a half-full FIFO. When the FIFO is full, any further shift-ins are disabled. When the FIFO is empty and OE is LOW, the falling edge of the first SI will cause the first data word just shifted-in to appear at the output, even though SO may be LOW. Shift-Out SO Data is read from the FIFO by the Shift-Out signal provided the FIFO is not empty. SO going HIGH causes OR to go LOW indicating that output stage is busy. On the falling edge of SO, new data reaches the output after propagation delay tD. If the last data has been shifted-out of the memory, OR continues to remain LOW, and the last word shifted-out remains on the output pins. Output Enable OE LOW enables the 3-STATE output buffers. When OE is HIGH, the outputs are in a 3-STATE mode. OUTPUTS Half-Full HF This status flag along with the FULL status flag indicates the degree of fullness of the FIFO. On reset, HF is LOW it rises on the falling edge of the first SI. The rising edge of the SI pulse that fills up the FIFO makes HF go LOW. Going from the empty to the full state with SO LOW, the falling edge of the first SI causes HF to go HIGH, the rising edge of the 33rd SI causes FULL to go HIGH, and the rising edge of the 64th SI causes HF to go LOW. When the FIFO is full, HF is LOW and the falling edge of the first shift-out causes HF to go HIGH indicating a “nonfull” FIFO. Full Flag FULL This status flag along with the HF status flag indicates the degree of fullness of the FIFO. On reset, FULL is LOW. When half the memory is filled, on the rising edge of the next SI, the FULL flag goes HIGH. It remains set until the difference between the write pointer and the read pointer is less than or equal to one-half of the total memory of the device. The FULL flag then goes LOW on the rising edge of the next SO. Status Flags Truth Table FULL Status Flag Condition L Empty H Full L <32 Locations Filled H Locations Filled H = HIGH Voltage Level L = LOW Voltage Level Reset Truth Table Inputs Outputs MR SI SO IR OR HF FULL LXXHL L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Data Outputs Data outputs are enabled when OE is LOW and in the 3STATE condition when OE is HIGH. Input Ready IR HIGH indicates data can be shifted-in. When SI goes HIGH, IR goes LOW, indicating input stage is busy. IR stays LOW when the FIFO is full and goes HIGH after the falling edge of the first shift-out. Output Ready OR HIGH indicates data can be shifted-out from the FIFO. When SO goes HIGH, OR goes LOW, indicating output stage is busy. OR is LOW when the FIFO is reset or empty and goes HIGH after the falling edge of the first shift-in.

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74ACT2708 64 x 9 First-In, First-Out Memory
74ACT2708 64 x 9 First-In, First-Out Memory

The ACT2708 is an expandable first-in, first-out memory organized as 64 words by 9 bits. An 85 MHz shift-in and 60 MHz shift-out typical data rate makes it ideal for high-speed applications. It uses a dual port RAM architecture with pointer logic to achieve the high speed with negligible fallthrough time.

Separate Shift-In SI and Shift-Out SO clocks control the use of synchronous or asynchronous write or read. Other controls include a Master Reset MR and Output Enable OE for initializing the internal registers and allowing the data outputs to be 3-STATE. Input Ready IR and Output Ready OR signal when the FIFO is ready for I/O operations. The status flags HF and FULL indicate when the FIFO is full, empty or half full.

The FIFO can be expanded to provide different word lengths by tying off unused data inputs.
s 64-words by 9-bit dual port RAM organization s 85 MHz shift-in, 60 MHz shift-out data rate, typical s Expandable in word width only s TTL-compatible inputs s Asynchronous or synchronous operation s Asynchronous master reset s Outputs source/sink 8 mA s 3-STATE outputs s Full ESD protection s Input and output pins directly in line for easy board lay-
out s TRW 1030 work-alike operation
• High-speed disk or tape controllers
• A/D output buffers
• High-speed graphics pixel buffer
• Video time base correction
• Digital filtering
Ordering Code:

Order Number Package Number

Package Description
74ACT2708PC

N28B
28-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-010, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Assignment for DIP

Pin Names MR OE SI SO IR OR HF FULL

Description Data Inputs Master Reset Output Enable Input Shift-In Shift-Out Input Ready Output Ready Half Full Flag Full Flag Data Outputs

FACT is a trademark of Fairchild Semiconductor Corporation.
1999 Fairchild Semiconductor Corporation DS010144.prf
74ACT2708

Logic Symbol Block Diagram
74ACT2708

Functional Description

INPUTS

Data Inputs Data inputs for 9-bit wide data are TTL-compatible. Word width can be reduced by trying unused inputs to ground and leaving the corresponding outputs open.

Reset MR Reset is accomplished by pulsing the MR input LOW. During normal operation MR is HIGH. A reset is required after power up to guarantee correct operation. On reset, the data outputs go LOW, IR goes HIGH, OR goes LOW, FH and FULL go LOW. During reset, both internal read and write pointers are set to the first location in the array.

Shift-In SI Data is written into the FIFO by pulsing SI HIGH. When Shift-In goes HIGH, the data is loaded into an internal data latch. Data setup and hold times need to be adhered to with respect to the falling edge of SI. The write cycle is complete after the falling edge of SI. The shift-in is independent of any ongoing shift-out operation. After the first word has been written into the FIFO, the falling edge of SI makes HF go HIGH, indicating a non-empty FIFO. The first data word appears at the output after the falling edge of SI. After half the memory is filled, the next rising edge of SI makes FULL go HIGH indicating a half-full FIFO. When the FIFO is full, any further shift-ins are disabled. When the FIFO is empty and OE is LOW, the falling edge of the first SI will cause the first data word just shifted-in to appear at the output, even though SO may be LOW.

Shift-Out SO Data is read from the FIFO by the Shift-Out signal provided the FIFO is not empty. SO going HIGH causes OR to go LOW indicating that output stage is busy. On the falling edge of SO, new data reaches the output after propagation delay tD. If the last data has been shifted-out of the memory, OR continues to remain LOW, and the last word shifted-out remains on the output pins.

Output Enable OE LOW enables the 3-STATE output buffers. When OE is HIGH, the outputs are in a 3-STATE mode.

OUTPUTS

Half-Full HF

This status flag along with the FULL status flag indicates the degree of fullness of the FIFO. On reset, HF is LOW it rises on the falling edge of the first SI. The rising edge of the SI pulse that fills up the FIFO makes HF go LOW. Going from the empty to the full state with SO LOW, the falling edge of the first SI causes HF to go HIGH, the rising edge of the 33rd SI causes FULL to go HIGH, and the rising edge of the 64th SI causes HF to go LOW.

When the FIFO is full, HF is LOW and the falling edge of the first shift-out causes HF to go HIGH indicating a “nonfull” FIFO.

Full Flag FULL

This status flag along with the HF status flag indicates the degree of fullness of the FIFO. On reset, FULL is LOW. When half the memory is filled, on the rising edge of the next SI, the FULL flag goes HIGH. It remains set until the difference between the write pointer and the read pointer is less than or equal to one-half of the total memory of the device. The FULL flag then goes LOW on the rising edge of the next SO.

Status Flags Truth Table

FULL

Status Flag Condition

L Empty

H Full

L <32 Locations Filled

H Locations Filled

H = HIGH Voltage Level L = LOW Voltage Level

Reset Truth Table

Inputs

Outputs

MR SI SO IR OR HF FULL

LXXHL L

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

Data Outputs Data outputs are enabled when OE is LOW and in the 3STATE condition when OE is HIGH.

Input Ready IR HIGH indicates data can be shifted-in. When SI goes HIGH, IR goes LOW, indicating input stage is busy. IR stays LOW when the FIFO is full and goes HIGH after the falling edge of the first shift-out.

Output Ready OR HIGH indicates data can be shifted-out from the FIFO. When SO goes HIGH, OR goes LOW, indicating output stage is busy. OR is LOW when the FIFO is reset or empty and goes HIGH after the falling edge of the first shift-in.

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Datasheet ID: 74ACT2708PC 513171