CY7C1471V33-117AXC

CY7C1471V33-117AXC Datasheet

CY7C1471V33 CY7C1473V33 CY7C1475V33

Part	Datasheet
CY7C1471V33-117AXC	CY7C1471V33-117AXC (pdf)

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CY7C1471V33 CY7C1473V33 CY7C1475V33 72-Mbit 2M x 36/4M x 18/1M x 72 Flow-Through SRAM with NoBL Architecture Functional Description[1] • No Bus Latency NoBL architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero wait states • Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation • Byte Write capability • 3.3V/2.5V I/O supply VDDQ • Fast clock-to-output times ns for 133-MHz device • Clock Enable CEN pin to enable clock and suspend operation • Synchronous self-timed writes • Asynchronous Output Enable • CY7C1471V33, CY7C1473V33 available in JEDEC-standard lead-free 100-pin TQFP, lead-free and non-lead-free 165-ball FBGA package. CY7C1475V33 available in lead-free and non-lead-free 209 ball FBGA package • Three chip enables for simple depth expansion • Automatic Power-down feature available using ZZ mode or CE deselect • IEEE JTAG Boundary Scan compatible • Burst or interleaved burst order • Low standby power The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are 3.3V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through Burst SRAMs designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are equipped with the advanced No Bus Latency NoBL logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which when deasserted suspends operation and extends the previous clock cycle.Maximum access delay from the clock rise is ns 133-MHz device . Write operations are controlled by the two or four Byte Write Select BWX and a Write Enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 133 MHz 117 MHz Unit Note For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 CY7C1471V33 CY7C1473V33 CY7C1475V33 Logic Block Diagram CY7C1471V33 2M x 36 A0, A1, A MODE ADDRESS REGISTER A1 A0 D1 D0 ADV/LD C WRITE ADDRESS REGISTER Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Part and Package Type Operating Range 133 CY7C1471V33-133AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Commercial CY7C1473V33-133AXC CY7C1471V33-133BZC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm CY7C1473V33-133BZC CY7C1471V33-133BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Lead-Free CY7C1473V33-133BZXC CY7C1475V33-133BGC 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm CY7C1475V33-133BGXC 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Lead-Free CY7C1471V33-133AXI 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free lndustrial CY7C1473V33-133AXI CY7C1471V33-133BZI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm CY7C1473V33-133BZI CY7C1471V33-133BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Lead-Free CY7C1473V33-133BZXI CY7C1475V33-133BGI 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm CY7C1475V33-133BGXI 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Lead-Free 117 CY7C1471V33-117AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Commercial CY7C1473V33-117AXC CY7C1471V33-117BZC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm CY7C1473V33-117BZC CY7C1471V33-117BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Lead-Free CY7C1473V33-117BZXC CY7C1475V33-117BGC 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm CY7C1475V33-117BGXC 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Lead-Free CY7C1471V33-117AXI 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free lndustrial CY7C1473V33-117AXI CY7C1471V33-117BZI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm CY7C1473V33-117BZI CY7C1471V33-117BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Lead-Free CY7C1473V33-117BZXI Updated ordering information Changed Advanced Information to Preliminary 223721 See ECN NJY Changed timing diagrams Changed logic block diagrams Modified Functional Description Modified “Functional Overview” section Added boundary scan order for all packages Included thermal numbers and capacitance values for all packages Removed 150-MHz speed grade offering Included ISB and IDD values Changed package outline for 165FBGA package and 209-ball BGA package Removed 119-BGA package offering 235012 See ECN RYQ Minor Change The data sheets do not match on the spec system and external web 243572 See ECN NJY Changed ball H2 from VDD to NC in the 165-ball FBGA package in page 6 Modified capacitance values on page 21 299511 See ECN SYT Removed 117-MHz Speed Bin Changed ΘJA from to °C/W and ΘJC from to °C/W for 100 TQFP Package on Page # 21 Added lead-free information for 100-Pin TQFP, 165 FBGA and 209 BGA Packages Added comment of ‘Lead-free BG packages availability’ below the Ordering Information 320197 See ECN PCI Corrected part number typos in the logic block diagram on page# 2 331513 See ECN PCI Address expansion pins/balls in the pinouts for all packages are modified as per JEDEC standard Added Address Expansion pins in the Pin Definitions Table Added Industrial Operating Range Modified VOL, VOH Test Conditions Updated Ordering Information Table 416221 See ECN RXU Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Removed 100MHz Speed bin & Added 117MHz Speed bin Changed the description of IX from Input Load Current to Input Leakage Current on page# 19 Changed the IX current values of MODE on page # 19 from µA and 30 µA to µA and 5 µA Changed the IX current values of ZZ on page # 19 from µA and 5 µA to µA and 30 µA Changed VIH < VDD to VIH < VDD on page # 19 Replaced Package Name column with Package Diagram in the Ordering Information table Updated the Ordering Information Table 472335 See ECN VKN Corrected the typo in the pin configuration for 209-Ball FBGA pinout Corrected the ball name for H9 to VSS from VSSQ . Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND. Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table. Updated the Ordering Information table. Page 29 of 29

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CY7C1471V33 CY7C1473V33 CY7C1475V33
72-Mbit 2M x 36/4M x 18/1M x 72 Flow-Through SRAM with NoBL Architecture

Functional Description[1]
• No Bus Latency NoBL architecture eliminates dead cycles between write and read cycles
• Can support up to 133-MHz bus operations with zero wait states
• Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 3.3V/2.5V I/O supply VDDQ
• Fast clock-to-output times
ns for 133-MHz device
• Clock Enable CEN pin to enable clock and suspend operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• CY7C1471V33, CY7C1473V33 available in JEDEC-standard lead-free 100-pin TQFP, lead-free and non-lead-free 165-ball FBGA package. CY7C1475V33 available in lead-free and non-lead-free 209 ball FBGA package
• Three chip enables for simple depth expansion
• Automatic Power-down feature available using ZZ mode or CE deselect
• IEEE JTAG Boundary Scan compatible
• Burst or interleaved burst order
• Low standby power

The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are 3.3V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through Burst SRAMs designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are equipped with the advanced No Bus Latency NoBL logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which when deasserted suspends operation and extends the previous clock cycle.Maximum access delay from the clock rise is ns 133-MHz device .

Write operations are controlled by the two or four Byte Write Select BWX and a Write Enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.

Selection Guide

Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current
133 MHz
117 MHz

Unit

Note For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600

CY7C1471V33 CY7C1473V33 CY7C1475V33

Logic Block Diagram CY7C1471V33 2M x 36

A0, A1, A

MODE

ADDRESS REGISTER

A1 A0

D1 D0

ADV/LD C

WRITE ADDRESS REGISTER
Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Part and Package Type

Operating Range
133 CY7C1471V33-133AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free

Commercial

CY7C1473V33-133AXC

CY7C1471V33-133BZC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm

CY7C1473V33-133BZC

CY7C1471V33-133BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Lead-Free

CY7C1473V33-133BZXC

CY7C1475V33-133BGC 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm

CY7C1475V33-133BGXC
209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Lead-Free

CY7C1471V33-133AXI 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free
lndustrial

CY7C1473V33-133AXI

CY7C1471V33-133BZI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm

CY7C1473V33-133BZI

CY7C1471V33-133BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Lead-Free

CY7C1473V33-133BZXI

CY7C1475V33-133BGI 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm

CY7C1475V33-133BGXI
209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Lead-Free
117 CY7C1471V33-117AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free

Commercial

CY7C1473V33-117AXC

CY7C1471V33-117BZC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm

CY7C1473V33-117BZC

CY7C1471V33-117BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Lead-Free

CY7C1473V33-117BZXC

CY7C1475V33-117BGC 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm

CY7C1475V33-117BGXC
209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Lead-Free

CY7C1471V33-117AXI 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free
lndustrial

CY7C1473V33-117AXI

CY7C1471V33-117BZI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm

CY7C1473V33-117BZI

CY7C1471V33-117BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Lead-Free

CY7C1473V33-117BZXI
Updated ordering information

Changed Advanced Information to Preliminary
223721 See ECN NJY Changed timing diagrams

Changed logic block diagrams

Modified Functional Description

Modified “Functional Overview” section

Added boundary scan order for all packages

Included thermal numbers and capacitance values for all packages

Removed 150-MHz speed grade offering

Included ISB and IDD values

Changed package outline for 165FBGA package and 209-ball BGA package

Removed 119-BGA package offering
235012 See ECN RYQ Minor Change The data sheets do not match on the spec system and
external web
243572 See ECN

NJY Changed ball H2 from VDD to NC in the 165-ball FBGA package in page 6

Modified capacitance values on page 21
299511 See ECN SYT Removed 117-MHz Speed Bin

Changed ΘJA from to °C/W and ΘJC from to °C/W for 100 TQFP Package on Page # 21

Added lead-free information for 100-Pin TQFP, 165 FBGA and 209 BGA

Packages
Added comment of ‘Lead-free BG packages availability’ below the Ordering

Information
320197 See ECN

PCI Corrected part number typos in the logic block diagram on page# 2
331513 See ECN

PCI Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard

Added Address Expansion pins in the Pin Definitions Table

Added Industrial Operating Range
Modified VOL, VOH Test Conditions Updated Ordering Information Table
416221 See ECN RXU Converted from Preliminary to Final

Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”

Removed 100MHz Speed bin & Added 117MHz Speed bin

Changed the description of IX from Input Load Current to Input Leakage Current on page# 19

Changed the IX current values of MODE on page # 19 from µA and 30 µA to µA and 5 µA

Changed the IX current values of ZZ on page # 19 from µA and 5 µA to µA and 30 µA
Changed VIH < VDD to VIH < VDD on page # 19 Replaced Package Name column with Package Diagram in the Ordering

Information table
Updated the Ordering Information Table
472335 See ECN VKN Corrected the typo in the pin configuration for 209-Ball FBGA pinout

Corrected the ball name for H9 to VSS from VSSQ . Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND. Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table.
Updated the Ordering Information table.

Page 29 of 29

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Datasheet ID: CY7C1471V33-117AXC 508045