CY7C1471V25-133AXC

CY7C1471V25-133AXC Datasheet

CY7C1471BV25 CY7C1473BV25, CY7C1475BV25

Part	Datasheet
CY7C1471V25-133AXC	CY7C1471V25-133AXC (pdf)

Related Parts	Information
CY7C1471BV25-133AXCT	CY7C1471BV25-133AXCT
CY7C1471BV25-133AXC	CY7C1471BV25-133AXC
CY7C1471V25-133AXCT	CY7C1471V25-133AXCT

PDF Datasheet Preview
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 72-Mbit 2M x 36/4M x 18/1M x 72 Flow-Through SRAM with NoBL Architecture Functional Description • No Bus Latency NoBL architecture eliminates dead cycles between write and read cycles • Supports up to 133 MHz bus operations with zero wait states • Data transfers on every clock • Pin compatible and functionally equivalent to ZBT devices • Internally self timed output buffer control to eliminate the need to use OE • Registered inputs for flow through operation • Byte Write capability • 2.5V IO supply VDDQ • Fast clock-to-output times ns for 133-MHz device • Clock Enable CEN pin to enable clock and suspend operation • Synchronous self timed writes • Asynchronous Output Enable OE • CY7C1471BV25, CY7C1473BV25 available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 165-ball FBGA package. CY7C1475BV25 available in Pb-free and non-Pb-free 209-ball FBGA package. • Three Chip Enables CE1, CE2, CE3 for simple depth expansion. • Automatic power down feature available using ZZ mode or CE deselect. • IEEE JTAG Boundary Scan compatible • Burst Capability - linear or interleaved burst order • Low standby power The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 are 2.5V, 2M x 36/4M x 18/1M x 72 synchronous flow through burst SRAMs designed specifically to support unlimited true back-to-back read or write operations without the insertion of wait states. The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 are equipped with the advanced No Bus Latency NoBL logic required to enable consecutive read or write operations with data transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is ns 133-MHz device . Write operations are controlled by two or four Byte Write Select BWX and a Write Enable WE input. All writes are conducted with on-chip synchronous self timed write circuitry. Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide easy bank selection and output tri-state control. To avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Selection Guide 133 MHz 100 MHz Unit Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Logic Block Diagram CY7C1471BV25 2M x 36 A0, A1, A MODE ADDRESS REGISTER A1 A0 D1 D0 ADV/LD C WRITE ADDRESS REGISTER BURST LOGIC Q1 A1' Q0 A0' ADV/LD BW A BW B BW C BW D WE WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC MEMORY WRITE ARRAY DRIVERS OE CE1 READ LOGIC SLEEP CONTROL Logic Block Diagram CY7C1473BV25 4M x 18 A0, A1, A Ordering Information Cypress offers other versions of this type of product in different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at and refer to the product summary page at or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at Speed MHz Ordering Code 133 CY7C1471BV25-133AXC CY7C1471BV25-133AXI Package Diagram Part and Package Type 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free Operating Range Commercial lndustrial Page 26 of 30 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Package Diagrams Figure 100-Pin Thin Plastic Quad Flatpack 14 x 20 x mm , 51-85050 51-85050-C Page 27 of 30 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Package Diagrams continued Figure 165-Ball FBGA 15 x 17 x mm , 51-85165 51-85165-B Page 28 of 30 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Package Diagrams continued Figure 209-Ball FBGA 14 x 22 x mm , 51-85167 51-85167-*A Page 29 of 30 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document History Page Document Title CY7C1471BV25/CY7C1473BV25/CY7C1475BV25, 72-Mbit 2M x 36/4M x 18/1M x 72 Flow-Through SRAM with NoBL Architecture Document Number 001-15013 Orig. of Change Description of Change 1024500 See ECN VKN/KKVTMP New Data Sheet 1274731 See ECN VKN/AESA Corrected typo in the “NOP, STALL and DESELECT Cycles” waveform 1562503 See ECN VKN/AESA Removed 1.8V IO offering from the data sheet 1897447 See ECN VKN/AESA Added footnote 14 related to IDD 2082487 See ECN Converted from preliminary to final 2159486 See ECN VKN/PYRS Minor Change-Moved to the external web 2898501 03/24/2010 Removed inactive part numbers from Ordering Information table Updated package diagrams. Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 30 of 30 NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY7C1471BV25 CY7C1473BV25, CY7C1475BV25
72-Mbit 2M x 36/4M x 18/1M x 72 Flow-Through SRAM with NoBL Architecture

Functional Description
• No Bus Latency NoBL architecture eliminates dead cycles between write and read cycles
• Supports up to 133 MHz bus operations with zero wait states
• Data transfers on every clock
• Pin compatible and functionally equivalent to ZBT devices
• Internally self timed output buffer control to eliminate the need
to use OE
• Registered inputs for flow through operation
• Byte Write capability
• 2.5V IO supply VDDQ
• Fast clock-to-output times
ns for 133-MHz device
• Clock Enable CEN pin to enable clock and suspend operation
• Synchronous self timed writes
• Asynchronous Output Enable OE
• CY7C1471BV25, CY7C1473BV25 available in

JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 165-ball FBGA package. CY7C1475BV25 available in Pb-free and non-Pb-free 209-ball FBGA package.
• Three Chip Enables CE1, CE2, CE3 for simple depth expansion.
• Automatic power down feature available using ZZ mode or CE deselect.
• IEEE JTAG Boundary Scan compatible
• Burst Capability - linear or interleaved burst order
• Low standby power

The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 are 2.5V, 2M x 36/4M x 18/1M x 72 synchronous flow through burst SRAMs designed specifically to support unlimited true back-to-back read or write operations without the insertion of wait states. The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 are equipped with the advanced No Bus Latency NoBL logic required to enable consecutive read or write operations with data transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is ns 133-MHz device . Write operations are controlled by two or four Byte Write Select BWX and a Write Enable WE input. All writes are conducted with on-chip synchronous self timed write circuitry. Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide easy bank selection and output tri-state control. To avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.

Selection Guide
133 MHz
100 MHz

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C1471BV25 CY7C1473BV25, CY7C1475BV25

Logic Block Diagram CY7C1471BV25 2M x 36

A0, A1, A

MODE

ADDRESS REGISTER

A1 A0

D1 D0

ADV/LD C

WRITE ADDRESS REGISTER

BURST LOGIC

Q1 A1' Q0 A0'

ADV/LD BW A BW B BW C BW D WE

WRITE REGISTRY AND DATA COHERENCY

CONTROL LOGIC

MEMORY

WRITE

ARRAY

DRIVERS

OE CE1

READ LOGIC

SLEEP CONTROL

Logic Block Diagram CY7C1473BV25 4M x 18

A0, A1, A
Ordering Information

Cypress offers other versions of this type of product in different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at and refer to the product summary page at or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at

Speed MHz
Ordering Code
133 CY7C1471BV25-133AXC

CY7C1471BV25-133AXI

Package Diagram

Part and Package Type
51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free
51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free

Operating Range

Commercial lndustrial

Page 26 of 30 [+] Feedback

CY7C1471BV25 CY7C1473BV25, CY7C1475BV25

Package Diagrams

Figure 100-Pin Thin Plastic Quad Flatpack 14 x 20 x mm , 51-85050
51-85050-*C

Page 27 of 30 [+] Feedback

CY7C1471BV25 CY7C1473BV25, CY7C1475BV25

Package Diagrams continued

Figure 165-Ball FBGA 15 x 17 x mm , 51-85165
51-85165-*B

Page 28 of 30 [+] Feedback

CY7C1471BV25 CY7C1473BV25, CY7C1475BV25

Package Diagrams continued

Figure 209-Ball FBGA 14 x 22 x mm , 51-85167
51-85167-*A

Page 29 of 30 [+] Feedback

CY7C1471BV25 CY7C1473BV25, CY7C1475BV25

Document History Page

Document Title CY7C1471BV25/CY7C1473BV25/CY7C1475BV25, 72-Mbit 2M x 36/4M x 18/1M x 72 Flow-Through SRAM with NoBL Architecture Document Number 001-15013

Orig. of Change

Description of Change
1024500 See ECN VKN/KKVTMP New Data Sheet
1274731 See ECN VKN/AESA Corrected typo in the “NOP, STALL and DESELECT Cycles” waveform
1562503 See ECN VKN/AESA Removed 1.8V IO offering from the data sheet
1897447 See ECN VKN/AESA Added footnote 14 related to IDD
2082487 See ECN

Converted from preliminary to final
2159486 See ECN VKN/PYRS Minor Change-Moved to the external web
2898501 03/24/2010
Removed inactive part numbers from Ordering Information table Updated
package diagrams.

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 30 of 30

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback

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Datasheet ID: CY7C1471V25-133AXC 508044