CY7C1474BV25-167BGCT

CY7C1474BV25-167BGCT Datasheet


CY7C1470BV25 CY7C1472BV25, CY7C1474BV25

Part Datasheet
CY7C1474BV25-167BGCT CY7C1474BV25-167BGCT CY7C1474BV25-167BGCT (pdf)
Related Parts Information
CY7C1474BV25-167BGC CY7C1474BV25-167BGC CY7C1474BV25-167BGC
CY7C1474BV25-200BGIT CY7C1474BV25-200BGIT CY7C1474BV25-200BGIT
CY7C1470BV25-167BZCT CY7C1470BV25-167BZCT CY7C1470BV25-167BZCT
CY7C1470BV25-200BZIT CY7C1470BV25-200BZIT CY7C1470BV25-200BZIT
CY7C1470BV25-167BZI CY7C1470BV25-167BZI CY7C1470BV25-167BZI
CY7C1470BV25-167BZIT CY7C1470BV25-167BZIT CY7C1470BV25-167BZIT
CY7C1470BV25-200BZC CY7C1470BV25-200BZC CY7C1470BV25-200BZC
CY7C1470BV25-200BZCT CY7C1470BV25-200BZCT CY7C1470BV25-200BZCT
CY7C1470BV25-200BZI CY7C1470BV25-200BZI CY7C1470BV25-200BZI
CY7C1472BV25-200BZI CY7C1472BV25-200BZI CY7C1472BV25-200BZI
CY7C1472BV25-250BZC CY7C1472BV25-250BZC CY7C1472BV25-250BZC
CY7C1474BV25-167BGI CY7C1474BV25-167BGI CY7C1474BV25-167BGI
CY7C1474BV25-167BGIT CY7C1474BV25-167BGIT CY7C1474BV25-167BGIT
CY7C1474BV25-200BGC CY7C1474BV25-200BGC CY7C1474BV25-200BGC
CY7C1474BV25-200BGCT CY7C1474BV25-200BGCT CY7C1474BV25-200BGCT
CY7C1474BV25-200BGI CY7C1474BV25-200BGI CY7C1474BV25-200BGI
CY7C1470BV25-167BZC CY7C1470BV25-167BZC CY7C1470BV25-167BZC
CY7C1472BV25-200BZIT CY7C1472BV25-200BZIT CY7C1472BV25-200BZIT
CY7C1474BV25-200BGXI CY7C1474BV25-200BGXI CY7C1474BV25-200BGXI
CY7C1470BV25-167BZXC CY7C1470BV25-167BZXC CY7C1470BV25-167BZXC
PDF Datasheet Preview
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25
72-Mbit 2M x 36/4M x 18/1M x 72 Pipelined SRAM with NoBL Architecture
• Pin-compatible and functionally equivalent to ZBT
• Supports 250 MHz bus operations with zero wait states Available speed grades are 250, 200, and 167 MHz
• Internally self-timed output buffer control to eliminate the need to use asynchronous OE
• Fully registered inputs and outputs for pipelined operation
• Byte Write capability
• Single 2.5V power supply
• 2.5V IO supply VDDQ
• Fast clock-to-output times
ns for 250-MHz device
• Clock Enable CEN pin to suspend operation
• Synchronous self-timed writes
• CY7C1470BV25, CY7C1472BV25 available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 165-ball FBGA package. CY7C1474BV25 available in Pb-free and non-Pb-free 209-ball FBGA package
• IEEE JTAG Boundary Scan compatible
• Burst or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option

Functional Description

The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are 2.5V, 2M x 36/4M x 18/1M x 72 synchronous pipelined burst SRAMs with No Bus Latency NoBL logic, respectively. They are designed to support unlimited true back-to-back read or write operations with no wait states. The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are equipped with the advanced NoBL logic required to enable consecutive read or write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent read or write transitions. The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are pin-compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the Byte Write Selects for CY7C1470BV25, for CY7C1472BV25, and for CY7C1474BV25 and a Write Enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tri-state control. To avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.

Selection Guide

Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current
250 MHz 450 120
200 MHz 450 120
167 MHz

Unit
• San Jose, CA 95134-1709
• 408-943-2600
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CY7C1470BV25 CY7C1472BV25, CY7C1474BV25

Logic Block Diagram CY7C1470BV25 2M x 36

A0, A1, A

MODE

ADV/LD

BW a BW b BW c BW d

OE CE1 CE2 CE3

ADDRESS REGISTER 0

WRITE ADDRESS REGISTER 1

A1 D1

Q1 A1'

A0 D0 BURST Q0 A0'

LOGIC

ADV/LD
Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Part and Package Type

Operating Range
167 CY7C1470BV25-167AXC 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free

Commercial

CY7C1472BV25-167AXC

CY7C1470BV25-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm

CY7C1472BV25-167BZC

CY7C1470BV25-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1472BV25-167BZXC

CY7C1474BV25-167BGC 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm

CY7C1474BV25-167BGXC
209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Pb-Free

CY7C1470BV25-167AXI
51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free
lndustrial

CY7C1472BV25-167AXI

CY7C1470BV25-167BZI
51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm

CY7C1472BV25-167BZI

CY7C1470BV25-167BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1472BV25-167BZXI

CY7C1474BV25-167BGI 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm

CY7C1474BV25-167BGXI
209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Pb-Free
200 CY7C1470BV25-200AXC 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free

Commercial

CY7C1472BV25-200AXC

CY7C1470BV25-200BZC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm

CY7C1472BV25-200BZC

CY7C1470BV25-200BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1472BV25-200BZXC

CY7C1474BV25-200BGC 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm

CY7C1474BV25-200BGXC
209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Pb-Free

CY7C1470BV25-200AXI
51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free
lndustrial

CY7C1472BV25-200AXI

CY7C1470BV25-200BZI
Ordering Information continued

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Part and Package Type

Operating Range
250 CY7C1470BV25-250AXC 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free

Commercial

CY7C1472BV25-250AXC

CY7C1470BV25-250BZC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm

CY7C1472BV25-250BZC

CY7C1470BV25-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1472BV25-250BZXC

CY7C1474BV25-250BGC 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm

CY7C1474BV25-250BGXC
209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Pb-Free

CY7C1470BV25-250AXI
51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free

Industrial

CY7C1472BV25-250AXI

CY7C1470BV25-250BZI
51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm

CY7C1472BV25-250BZI

CY7C1470BV25-250BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1472BV25-250BZXI

CY7C1474BV25-250BGI 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm

CY7C1474BV25-250BGXI
209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Pb-Free

Page 25 of 29 [+] Feedback

CY7C1470BV25 CY7C1472BV25, CY7C1474BV25

Package Diagrams

Figure 100-Pin Thin Plastic Quad Flatpack 14 x 20 x mm , 51-85050
100 1
81 80

R MIN. MAX.

GAUGE PLANE
0° -7°

REF.
30 31
0° MIN.

R MIN. MAX.

MIN.

DETAIL A
More datasheets: 26012 | 0RQB-C0U12CG | 416 | 17801-T02 | 2819 | IRM-8755K-1 | LF-A-500 | DM74ALS165N | CY7C1474BV25-167BGC | CY7C1474BV25-200BGIT


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Datasheet ID: CY7C1474BV25-167BGCT 508043