DM74ALS165N
DM74ALS165N Datasheet
DM74ALS165 8-Bit Parallel In/Serial Out Shift Register
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DM74ALS165N |
DM74ALS165N (pdf) |
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| DM74ALS165 8-Bit Parallel In/Serial Out Shift Register DM74ALS165 8-Bit Parallel In/Serial Out Shift Register The DM74ALS165 is an 8-bit serial register that, when clocked, shifts the data toward serial output, QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the SH/LD input. The DM74ALS165 also features a clock inhibit function and a complemented serial output, QH. Clocking is accomplished by a LOW-to-HIGH transition of the CLK input while SH/LD is held HIGH and CLK INH is held LOW. The functions of the CLK and CLK INH clock inhibit inputs are interchangeable. Since a LOW CLK input and a LOW-to-HIGH transition of CLK INH will also accomplish clocking, CLK INH should be changed to the high level only while the CLK input is HIGH. Parallel loading is inhibited when SH/LD is held HIGH. The parallel inputs to the register are enabled while SH/LD is LOW independently of the levels of CLK, CLK INH, or SER inputs. s Complementary outputs s Direct overriding load data inputs s Gated clock inputs s Parallel-to-serial data conversion Ordering Code: Order Number Package Number Package Description DM74ALS165M M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow DM74ALS165N N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Internal Shift/ Clock Serial Parallel Outputs Output Load Inhibit A...H QA QB QH X a...h a b QA0 QB0 QH0 H QAn QGn L QAn QGn H QAn QGn L QAn QGn QA0 QB0 QH0 H = HIGH Level steady-state , L = LOW Level steady-state X = Don't Care any input, including transitions = Transition from LOW-to-HIGH level a...h = The level of steady-state input at inputs A through H, respectively QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established QAn, QGn = The level of QA or QG, respectively, before the most recent transition of the clock 2000 Fairchild Semiconductor Corporation DS006712 DM74ALS165 Logic Diagram Timing Diagram Typical Shift, Load, and Inhibit Sequences DM74ALS165 Absolute Maximum Ratings Note 1 Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Typical N Package M Package 7V 0°C to +70°C −65°C to +150°C 74.0°C/W 104.0°C/W Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions Parameter Units VCC VIH VIL IOH IOL fCLOCK tW Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency Pulse Duration |
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