CY7C1411BV18-250BZC
CY7C1411BV18-250BZC Datasheet
CY7C1411BV18, CY7C1426BV18 CY7C1413BV18, CY7C1415BV18
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CY7C1411BV18-250BZC |
CY7C1411BV18-250BZC (pdf) |
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| CY7C1411BV18, CY7C1426BV18 CY7C1413BV18, CY7C1415BV18 36-Mbit QDR -II SRAM 4-Word Burst Architecture • Separate independent read and write data ports Supports concurrent transactions • 300 MHz clock for high bandwidth • 4-word burst for reducing address bus frequency • Double Data Rate DDR interfaces on both read and write ports data transferred at 600 MHz at 300 MHz • Two input clocks K and K for precise DDR timing SRAM uses rising edges only • Two input clocks for output data C and C to minimize clock skew and flight time mismatches • Echo clocks CQ and CQ simplify data capture in high-speed systems • Single multiplexed address input bus latches address inputs for both read and write ports • Separate port selects for depth expansion • Synchronous internally self-timed writes • QDR-II operates with cycle read latency when DLL is enabled • Operates as a QDR-I device with 1 cycle read latency in DLL off mode • Available in x 8, x 9, x 18, and x 36 configurations • Full data coherency, providing most current data • Core VDD = ±0.1V IO VDDQ = 1.4V to VDD • Available in 165-Ball FBGA package 15 x 17 x mm • Offered in both Pb-free and non Pb-free packages • Variable drive HSTL output buffers • JTAG compatible test access port • Delay Lock Loop DLL for accurate data placement Configurations CY7C1411BV18 4M x 8 CY7C1426BV18 4M x 9 CY7C1413BV18 2M x 18 CY7C1415BV18 1M x 36 Functional Description The CY7C1411BV18, CY7C1426BV18, CY7C1413BV18, and CY7C1415BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR -II architecture. QDR-II architecture consists of two separate ports to access the memory array. The read port has dedicated data outputs to support the read operations and the write port has dedicated data inputs to support the write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common IO devices. Access to each port is through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input K clock. Accesses to the QDR-II read and write ports are completely independent of one another. To maximize data throughput, read and write ports are equipped with DDR interfaces. Each address location is associated with four 8-bit words CY7C1411BV18 , 9-bit words CY7C1426BV18 , 18-bit words CY7C1413BV18 , or 36-bit words CY7C1415BV18 that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks K and K and C and C , memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds.” Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on chip synchronous self-timed write circuitry. Selection Guide Description Maximum Operating Frequency Maximum Operating Current 300 MHz 1040 278 MHz 278 815 830 865 950 250 MHz 250 745 760 790 870 200 MHz 200 620 655 715 167 MHz 167 535 565 615 Unit MHz mA • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Logic Block Diagram CY7C1411BV18 CY7C1411BV18, CY7C1426BV18 CY7C1413BV18, CY7C1415BV18 D[7:0] Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Package Type Operating Range 300 CY7C1411BV18-300BZC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial CY7C1426BV18-300BZC CY7C1413BV18-300BZC CY7C1415BV18-300BZC CY7C1411BV18-300BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1426BV18-300BZXC CY7C1413BV18-300BZXC CY7C1415BV18-300BZXC CY7C1411BV18-300BZI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Industrial CY7C1426BV18-300BZI CY7C1413BV18-300BZI CY7C1415BV18-300BZI CY7C1411BV18-300BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1426BV18-300BZXI CY7C1413BV18-300BZXI CY7C1415BV18-300BZXI 278 CY7C1411BV18-278BZC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial CY7C1426BV18-278BZC CY7C1413BV18-278BZC CY7C1415BV18-278BZC CY7C1411BV18-278BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1426BV18-278BZXC CY7C1413BV18-278BZXC CY7C1415BV18-278BZXC CY7C1411BV18-278BZI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Industrial CY7C1426BV18-278BZI Ordering Information continued Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Package Type Operating Range 250 CY7C1411BV18-250BZC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial CY7C1426BV18-250BZC CY7C1413BV18-250BZC CY7C1415BV18-250BZC CY7C1411BV18-250BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1426BV18-250BZXC CY7C1413BV18-250BZXC CY7C1415BV18-250BZXC CY7C1411BV18-250BZI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Industrial CY7C1426BV18-250BZI CY7C1413BV18-250BZI CY7C1415BV18-250BZI CY7C1411BV18-250BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1426BV18-250BZXI CY7C1413BV18-250BZXI CY7C1415BV18-250BZXI 200 CY7C1411BV18-200BZC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial CY7C1426BV18-200BZC CY7C1413BV18-200BZC CY7C1415BV18-200BZC CY7C1411BV18-200BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1426BV18-200BZXC CY7C1413BV18-200BZXC CY7C1415BV18-200BZXC CY7C1411BV18-200BZI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Industrial CY7C1426BV18-200BZI Ordering Information continued Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Package Type Operating Range 167 CY7C1411BV18-167BZC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial CY7C1426BV18-167BZC CY7C1413BV18-167BZC CY7C1415BV18-167BZC CY7C1411BV18-167BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1426BV18-167BZXC CY7C1413BV18-167BZXC CY7C1415BV18-167BZXC CY7C1411BV18-167BZI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Industrial CY7C1426BV18-167BZI CY7C1413BV18-167BZI CY7C1415BV18-167BZI CY7C1411BV18-167BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1426BV18-167BZXI CY7C1413BV18-167BZXI CY7C1415BV18-167BZXI Page 28 of 30 [+] Feedback Package Diagram CY7C1411BV18, CY7C1426BV18 CY7C1413BV18, CY7C1415BV18 Figure 165-ball FBGA 15 x 17 x mm , 51-85195 ! " # % & ' * + , 0 2 ! " # % & ' * + , 0 2 51-85195-*A Page 29 of 30 [+] Feedback CY7C1411BV18, CY7C1426BV18 CY7C1413BV18, CY7C1415BV18 Document History Page Document Title 36-Mbit QDR -II SRAM 4-Word Burst Architecture Document Number 001-07037 ECN NO. SUBMISSION DATE ORIG. OF CHANGE DESCRIPTION OF CHANGE |
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