CY7C1386C-167AC

CY7C1386C-167AC Datasheet

CY7C1386C CY7C1387C

Part	Datasheet
CY7C1386C-167AC	CY7C1386C-167AC (pdf)

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CY7C1386C CY7C1387C 18-Mb 512K x 36/1M x 18 Pipelined DCD Sync SRAM Functional Description[1] • Supports bus operation up to 250 MHz • Available speed grades are 250, 225, 200 and 167 MHz • Registered inputs and outputs for pipelined operation • Optimal for performance Double-Cycle deselect • Depth expansion without wait state • 3.3V and +10% core power supply VDD • 2.5V / 3.3V I/O operation • Fast clock-to-output times ns for 250-MHz device ns for 225-MHz device ns for 200-MHz device ns for 167-MHz device • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting Pentium interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous output enable • Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA and 165-Ball fBGA packages • IEEE JTAG-Compatible Boundary Scan • “ZZ” Sleep Mode Option The CY7C1386C/CY7C1387C SRAM integrates 524,288 x 36 and 1048,576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, nAl WDCSrhitPipe, GW . Asynchronous inputs include the Output Enable OE and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV . Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations see Pin Descriptions and Truth Table for further details . Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed.This feature allows depth expansion without penalizing system performance. The CY7C1386C/CY7C1387C operates from a +3.3V core power supply while all outputs operate with a +3.3V or a +2.5V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide 250 MHz 225 MHz 200 MHz 167 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Notes For recommendations, please refer to the Cypress application note System Design Guidelines on CE3 and CE2 are for TQFP and 165 fBGA package only. 119 BGA is offered only in Single Chip Enable. Unit ns mA Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 CY7C1386C CY7C1387C Logic Block Diagram CY7C1386C 512K x 36 A0,A1,A MODE ADV CLK ADSC ADSP BWA BWE GW CE1 CE2 CE3 OE ADDRESS REGISTER 2 A[1:0] BURST Q1 COUNTER AND LOGIC DQD,DQPD BYTE WRITE REGISTER DQc,DQPC BYTE WRITE REGISTER DQB,DQPB BYTE WRITE REGISTER DQA,DQPA BYTE WRITE REGISTER Ordering Information Speed MHz Ordering Code Package Name Part and Package Type 250 CY7C1386C-250AC CY7C1387C-250AC A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables CY7C1386C-250BGC CY7C1387C-250BGC BG119 119-ball 14 x 22 x mm BGA 2 Chip Enables with JTAG CY7C1386C-250BZC CY7C1387C-250BZC BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables with JTAG 225 CY7C1386C-225AC CY7C1387C-225AC A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables CY7C1386C-225AI CY7C1387C-225AI CY7C1386C-225BGC CY7C1387C-225BGC BG119 119-ball 14 x 22 x mm BGA 2 Chip Enables with JTAG CY7C1386C-225BGI CY7C1387C-225BGI CY7C1386C-225BZC CY7C1387C-225BZC BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables with JTAG CY7C1386C-225BZI CY7C1387C-225BZI 200 CY7C1386C-200AC CY7C1387C-200AC A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables CY7C1386C-200AI CY7C1387C-200AI CY7C1386C-200BGC CY7C1387C-200BGC BG119 119-ball 14 x 22 x mm BGA 2 Chip Enables with JTAG CY7C1386C-200BGI CY7C1387C-200BGI CY7C1386C-200BZC CY7C1387C-200BZC BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables with JTAG CY7C1386C-200BZI CY7C1387C-200BZI 167 CY7C1386C-167AC CY7C1387C-167AC A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables CY7C1386C-167AI CY7C1387C-167AI CY7C1386C-167BGC CY7C1387C-167BGC BG119 119-ball 14 x 22 x mm BGA 2 Chip Enables with JTAG CY7C1386C-167BG ICY7C1387C-167BGI CY7C1386C-167BZC CY7C1387C-167BGC BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables with JTAG

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CY7C1386C CY7C1387C
18-Mb 512K x 36/1M x 18 Pipelined DCD Sync SRAM

Functional Description[1]
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 225, 200 and 167 MHz
• Registered inputs and outputs for pipelined operation
• Optimal for performance Double-Cycle deselect
• Depth expansion without wait state
• 3.3V and +10% core power supply VDD
• 2.5V / 3.3V I/O operation
• Fast clock-to-output times
ns for 250-MHz device ns for 225-MHz device ns for 200-MHz device ns for 167-MHz device
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA and 165-Ball fBGA packages
• IEEE JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode Option

The CY7C1386C/CY7C1387C SRAM integrates 524,288 x 36 and 1048,576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, nAl WDCSrhitPipe, GW . Asynchronous inputs include the Output Enable OE and the ZZ pin.

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV .

Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations see Pin Descriptions and Truth Table for further details . Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed.This feature allows depth expansion without penalizing system performance.

The CY7C1386C/CY7C1387C operates from a +3.3V core power supply while all outputs operate with a +3.3V or a +2.5V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.

Selection Guide
250 MHz
225 MHz
200 MHz
167 MHz

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.

Notes For recommendations, please refer to the Cypress application note System Design Guidelines on CE3 and CE2 are for TQFP and 165 fBGA package only. 119 BGA is offered only in Single Chip Enable.

Unit ns mA

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600

CY7C1386C CY7C1387C

Logic Block Diagram CY7C1386C 512K x 36

A0,A1,A MODE

ADV CLK

ADSC ADSP

BWA BWE GW

CE1 CE2 CE3 OE

ADDRESS REGISTER
2 A[1:0]

BURST Q1

COUNTER AND

LOGIC

DQD,DQPD BYTE

WRITE REGISTER

DQc,DQPC BYTE

WRITE REGISTER

DQB,DQPB BYTE

WRITE REGISTER

DQA,DQPA BYTE

WRITE REGISTER
Ordering Information

Speed MHz
Ordering Code

Package Name

Part and Package Type
250 CY7C1386C-250AC CY7C1387C-250AC

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables

CY7C1386C-250BGC CY7C1387C-250BGC

BG119 119-ball 14 x 22 x mm BGA 2 Chip Enables with JTAG

CY7C1386C-250BZC CY7C1387C-250BZC

BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables with JTAG
225 CY7C1386C-225AC CY7C1387C-225AC

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables

CY7C1386C-225AI CY7C1387C-225AI

CY7C1386C-225BGC CY7C1387C-225BGC

BG119 119-ball 14 x 22 x mm BGA 2 Chip Enables with JTAG

CY7C1386C-225BGI

CY7C1387C-225BGI

CY7C1386C-225BZC CY7C1387C-225BZC

BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables with JTAG

CY7C1386C-225BZI

CY7C1387C-225BZI
200 CY7C1386C-200AC CY7C1387C-200AC

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables

CY7C1386C-200AI CY7C1387C-200AI

CY7C1386C-200BGC CY7C1387C-200BGC

BG119 119-ball 14 x 22 x mm BGA 2 Chip Enables with JTAG

CY7C1386C-200BGI

CY7C1387C-200BGI

CY7C1386C-200BZC CY7C1387C-200BZC

BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables with JTAG

CY7C1386C-200BZI

CY7C1387C-200BZI
167 CY7C1386C-167AC CY7C1387C-167AC

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables

CY7C1386C-167AI

CY7C1387C-167AI

CY7C1386C-167BGC CY7C1387C-167BGC

BG119 119-ball 14 x 22 x mm BGA 2 Chip Enables with JTAG

CY7C1386C-167BG

ICY7C1387C-167BGI

CY7C1386C-167BZC CY7C1387C-167BGC

BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables with JTAG

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Datasheet ID: CY7C1386C-167AC 508006