74VHCT373ASJ

74VHCT373ASJ Datasheet

74VHCT373A Octal D-Type Latch with 3-STATE Outputs

Part	Datasheet
74VHCT373ASJ	74VHCT373ASJ (pdf)

Related Parts	Information
74VHCT373AMTCX	74VHCT373AMTCX
74VHCT373AMTC	74VHCT373AMTC
74VHCT373AN	74VHCT373AN
74VHCT373AMX	74VHCT373AMX
74VHCT373AM	74VHCT373AM
74VHCT373ASJX	74VHCT373ASJX
74VHCT373M	74VHCT373M

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74VHCT373A Octal D-Type Latch with 3-STATE Outputs 74VHCT373A Octal D-Type Latch with 3-STATE Outputs May 2007 • High speed tPD = 7.7ns Typ. at TA = 25°C • High Noise Immunity VIH = 2.0V, VIL = 0.8V • Power Down Protection is provided on all inputs and outputs • Low Power Dissipation ICC = 4µA Max. TA = 25°C • Pin and Function Compatible with 74HCT373 The VHCT373A is an advanced high speed CMOS octal D-type latch with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input LE and an output enable input OE . The latches appear transparent to data when latch enable LE is HIGH. When LE is LOW, the data that meets the setup time is latched. When the OE input is HIGH, the eight outputs are in a high impedance state. Protection circuits ensure that 0V to 7V can be applied to the input and output 1 pins without regard to the supply voltage. This device can be used to interface 3V to 5V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. Note Outputs in OFF-State Ordering Information Order Number 74VHCT373AM 74VHCT373ASJ 74VHCT373AMTC Package Number M20B M20D MTC20 Package Description 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering number. Pb-Free package per JEDEC J-STD-020B. 74VHCT373A Octal D-Type Latch with 3-STATE Outputs Connection Diagram Logic Symbol IEEE/IEC Pin Description Pin Names LE OE Description Data Inputs Latch Enable Input Output Enable Input 3-STATE Outputs Truth Table Inputs Outputs H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable 1997 Fairchild Semiconductor Corporation 74VHCT373A Octal D-Type Latch with 3-STATE Outputs Functional Description The VHCT373A contains eight D-type latches with 3-STATE standard outputs. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable OE input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 1997 Fairchild Semiconductor Corporation 74VHCT373A Octal D-Type Latch with 3-STATE Outputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC VIN VOUT IIK IOK IOUT ICC TSTG TL Parameter Supply Voltage DC Input Voltage DC Output Voltage Note 2 Note 3 Input Diode Current Output Diode Current 4 DC Output Current DC VCC / GND Current Storage Temperature Lead Temperature Soldering, 10 seconds Rating to +7.0V to +7.0V to VCC + 0.5V to +7.0V ±20mA ±25mA ±75mA to +150°C 260°C Recommended Operating Conditions 5 The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Parameter VCC VIN VOUT Supply Voltage Input Voltage Output Voltage Note 2 Note 3 TOPR tr, tf Operating Temperature Input Rise and Fall Time, VCC = 5.0V ± 0.5V Notes HIGH or LOW state. IOUT absolute maximum rating must be observed. When outputs are in OFF-State or when VCC = 0V. VOUT < GND, VOUT > VCC Outputs Active . Unused inputs must be held HIGH or LOW. They may not float. Rating 4.5V to +5.5V 0V to +5.5V 0V to VCC 0V to 5.5V to +85°C 0ns/V ~ 20ns/V

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74VHCT373A Octal D-Type Latch with 3-STATE Outputs
74VHCT373A Octal D-Type Latch with 3-STATE Outputs

May 2007
• High speed tPD = 7.7ns Typ. at TA = 25°C
• High Noise Immunity VIH = 2.0V, VIL = 0.8V
• Power Down Protection is provided on all inputs and
outputs
• Low Power Dissipation ICC = 4µA Max. TA = 25°C
• Pin and Function Compatible with 74HCT373

The VHCT373A is an advanced high speed CMOS octal D-type latch with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input LE and an output enable input OE . The latches appear transparent to data when latch enable LE is HIGH. When LE is LOW, the data that meets the setup time is latched. When the OE input is HIGH, the eight outputs are in a high impedance state.

Protection circuits ensure that 0V to 7V can be applied to the input and output 1 pins without regard to the supply voltage. This device can be used to interface 3V to 5V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages.

Note Outputs in OFF-State
Ordering Information

Order Number 74VHCT373AM 74VHCT373ASJ 74VHCT373AMTC

Package Number

M20B M20D MTC20

Package Description 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering number. Pb-Free package per JEDEC J-STD-020B.
74VHCT373A Octal D-Type Latch with 3-STATE Outputs

Connection Diagram

Logic Symbol

IEEE/IEC

Pin Description

Pin Names LE OE

Description Data Inputs Latch Enable Input Output Enable Input 3-STATE Outputs

Truth Table

Inputs

Outputs

H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
1997 Fairchild Semiconductor Corporation
74VHCT373A Octal D-Type Latch with 3-STATE Outputs

Functional Description

The VHCT373A contains eight D-type latches with 3-STATE standard outputs. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the

HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable OE input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
1997 Fairchild Semiconductor Corporation
74VHCT373A Octal D-Type Latch with 3-STATE Outputs

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Symbol VCC VIN VOUT

IIK IOK IOUT ICC TSTG TL

Parameter Supply Voltage DC Input Voltage DC Output Voltage

Note 2 Note 3 Input Diode Current Output Diode Current 4 DC Output Current DC VCC / GND Current Storage Temperature Lead Temperature Soldering, 10 seconds

Rating to +7.0V to +7.0V
to VCC + 0.5V to +7.0V ±20mA ±25mA ±75mA
to +150°C 260°C

Recommended Operating Conditions 5

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.

Parameter

VCC VIN VOUT

Supply Voltage Input Voltage Output Voltage

Note 2 Note 3

TOPR tr, tf

Operating Temperature Input Rise and Fall Time, VCC = 5.0V ± 0.5V

Notes HIGH or LOW state. IOUT absolute maximum rating must be observed. When outputs are in OFF-State or when VCC = 0V. VOUT < GND, VOUT > VCC Outputs Active . Unused inputs must be held HIGH or LOW. They may not float.

Rating 4.5V to +5.5V 0V to +5.5V
0V to VCC 0V to 5.5V to +85°C 0ns/V ~ 20ns/V

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Datasheet ID: 74VHCT373ASJ 513123