CY7C1381D-133BGXC

CY7C1381D-133BGXC Datasheet

CY7C1381D CY7C1383D

Part	Datasheet
CY7C1381D-133BGXC	CY7C1381D-133BGXC (pdf)

PDF Datasheet Preview
CY7C1381D CY7C1383D 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM Functional Description[1] • Supports 133-MHz bus operations • 512K x 36/1M x 18 common I/O • 3.3V and +10% core power supply VDD • 2.5V or 3.3V I/O supply VDDQ • Fast clock-to-output time ns 133-MHz version ns 100-MHz version • Provide high-performance 2-1-1-1 access rate • User-selectable burst counter supporting interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed write • Asynchronous output enable • Offered in JEDEC-standard lead-free 100-pin TQFP ,119-ball BGA and 165-ball fBGA packages • JTAG boundary scan for BGA and fBGA packages • “ZZ” Sleep Mode option The CY7C1381D/CY7C1383D is a 3.3V, 512K x 36 and 1 Mbit x 18 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is ns 133-MHz version . A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable CCoEn1tr o, EW2riatendECnaEb3l[e2]s , BBuWrsxt, and BWE , and Global Write GW . Asynchronous inputs include the Output Enable OE and the ZZ pin. The CY7C1381D/CY7C1383D allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe ADSP or the cache Controller Address Strobe ADSC inputs. Address advancement is controlled by the Address Advancement ADV input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV . The CY7C1381D/CY7C1383D operates from a +3.3V core power supply while all outputs may operate with either a or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide 133 MHz 100 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Notes For recommendations, please refer to the Cypress application note System Design Guidelines on CE3, CE2 are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable. Unit ns mA Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 CY7C1381D CY7C1383D Logic Block Diagram CY7C1381D 512K x 36 A0, A1, A MODE ADV CLK ADSC ADSP BWD BWA BWE GW CE1 CE2 CE3 OE ADDRESS REGISTER A[1:0] BURST Q1 COUNTER AND LOGIC DQD, DQPD BYTE WRITE REGISTER DQC, DQPC BYTE WRITE REGISTER DQB, DQPB BYTE WRITE REGISTER DQA, DQPA BYTE WRITE REGISTER ENABLE REGISTER DQD, DQPD BYTE WRITE REGISTER DQC, DQPC BYTE Ordering Information Speed MHz Ordering Code Package Name Part and Package Type Operating Range 133 CY7C1381D-133AXC CY7C1383D-133AXC A101 Lead-Free 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Commercial Chip Enables CY7C1381D-133BGC CY7C1383D-133BGC BG119 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG CY7C1381D-133BZC CY7C1383D-133BZC BB165D 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.4mm 3 Chip Enables and JTAG CY7C1381D-133BGXC BG119 Lead-Free 119-ball 14 x 22 x mm BGA 3 Chip Enables CY7C1383D-133BGXC and JTAG CY7C1381D-133BZXC BB165D Lead-Free 165-ball Fine-Pitch Ball Grid Array 13 x 15 x CY7C1383D-133BZXC 1.4mm 3 Chip Enables and JTAG 100 CY7C1381D-100AXC CY7C1383D-100AXC A101 Lead-Free 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Commercial Chip Enables CY7C1381D-100BGC BG119 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG CY7C1383D-100BGC CY7C1381D-100BZC CY7C1383D-100BZC BB165D 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.4mm 3 Chip Enables and JTAG CY7C1381D-100BGXC CY7C1383D-100BGXC BG119 Lead-Free 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG CY7C1381D-100BZXC BB165D Lead-Free 165-ball Fine-Pitch Ball Grid Array 13 x 15 x CY7C1383D-100BZXC 1.4mm 3 Chip Enables and JTAG Notes Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. DQs are in high-Z when exiting ZZ sleep mode. Page 25 of 29 CY7C1381D CY7C1383D Ordering Information continued Speed MHz Ordering Code 100 CY7C1381D-100AXI CY7C1383D-100AXI CY7C1381D-100BGI CY7C1383D-100BGI CY7C1381D-100BZI CY7C1383D-100BZI CY7C1381D-100BGXI CY7C1383D-100BGXI CY7C1381D-100BZXI CY7C1383D-100BZXI Package Name Part and Package Type A101 Lead-Free 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables BG119 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG BB165D 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.4mm 3 Chip Enables and JTAG BG119 Lead-Free 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG BB165D Lead-Free 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.4mm 3 Chip Enables and JTAG Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Lead-free BG packages ordering Code:BGX will be available in Package Diagrams 100-Pin Thin Plastic Quad Flatpack 14 x 20 x mm A101 Operating Range Industrial 100 1 81 80 DIMENSIONS ARE IN MILLIMETERS. R MIN. MAX. GAUGE PLANE 0° -7° REF. 30 31 0° MIN. R MIN. MAX. MIN. DETAIL A TYP. 51 50 STAND-OFF MIN. MAX. 12° ±1° 8X SEATING PLANE SEE DETAIL MAX. MAX. 51-85050-A Page 26 of 29 Package Diagrams continued 119-Lead PBGA 14 x 22 x mm BG119 CY7C1381D CY7C1383D 51-85115-B Page 27 of 29 Package Diagrams continued 165 FBGA 13 x 15 x MM BB165D CY7C1381D CY7C1383D 51-85180-** i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Page 28 of 29 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C1381D CY7C1383D Document History Page Document Title CY7C1381D/CY7C1383D 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM Document Number 38-05544 Added comment of ‘Lead-free BG packages availability’ below the Ordering Information Page 29 of 29

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CY7C1381D CY7C1383D
18-Mbit 512K x 36/1M x 18 Flow-Through SRAM

Functional Description[1]
• Supports 133-MHz bus operations
• 512K x 36/1M x 18 common I/O
• 3.3V and +10% core power supply VDD
• 2.5V or 3.3V I/O supply VDDQ
• Fast clock-to-output time
ns 133-MHz version ns 100-MHz version
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Offered in JEDEC-standard lead-free 100-pin TQFP ,119-ball BGA and 165-ball fBGA packages
• JTAG boundary scan for BGA and fBGA packages
• “ZZ” Sleep Mode option

The CY7C1381D/CY7C1383D is a 3.3V, 512K x 36 and 1 Mbit x 18 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is ns 133-MHz version . A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable CCoEn1tr o, EW2riatendECnaEb3l[e2]s , BBuWrsxt, and BWE , and Global Write GW . Asynchronous inputs include the Output Enable OE and the ZZ pin.

The CY7C1381D/CY7C1383D allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe ADSP or the cache Controller Address Strobe ADSC inputs. Address advancement is controlled by the Address Advancement ADV input.

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV .

The CY7C1381D/CY7C1383D operates from a +3.3V core power supply while all outputs may operate with either a or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.

Selection Guide
133 MHz
100 MHz

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

Notes For recommendations, please refer to the Cypress application note System Design Guidelines on CE3, CE2 are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.

Unit ns mA

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600

CY7C1381D CY7C1383D

Logic Block Diagram CY7C1381D 512K x 36

A0, A1, A MODE ADV CLK

ADSC ADSP BWD

BWA BWE

GW CE1 CE2 CE3 OE

ADDRESS REGISTER

A[1:0]

BURST Q1

COUNTER

AND LOGIC

DQD, DQPD BYTE

WRITE REGISTER

DQC, DQPC BYTE

WRITE REGISTER

DQB, DQPB BYTE

WRITE REGISTER

DQA, DQPA BYTE

WRITE REGISTER

ENABLE REGISTER

DQD, DQPD BYTE

WRITE REGISTER

DQC, DQPC BYTE
Ordering Information

Speed MHz
Ordering Code

Package Name

Part and Package Type

Operating Range
133 CY7C1381D-133AXC CY7C1383D-133AXC

A101 Lead-Free 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Commercial Chip Enables

CY7C1381D-133BGC CY7C1383D-133BGC

BG119 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG

CY7C1381D-133BZC CY7C1383D-133BZC

BB165D 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.4mm 3 Chip Enables and JTAG

CY7C1381D-133BGXC BG119 Lead-Free 119-ball 14 x 22 x mm BGA 3 Chip Enables

CY7C1383D-133BGXC
and JTAG

CY7C1381D-133BZXC BB165D Lead-Free 165-ball Fine-Pitch Ball Grid Array 13 x 15 x

CY7C1383D-133BZXC
1.4mm 3 Chip Enables and JTAG
100 CY7C1381D-100AXC CY7C1383D-100AXC

A101 Lead-Free 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Commercial Chip Enables

CY7C1381D-100BGC

BG119 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG

CY7C1383D-100BGC

CY7C1381D-100BZC CY7C1383D-100BZC

BB165D 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.4mm 3 Chip Enables and JTAG

CY7C1381D-100BGXC CY7C1383D-100BGXC

BG119 Lead-Free 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG

CY7C1381D-100BZXC BB165D Lead-Free 165-ball Fine-Pitch Ball Grid Array 13 x 15 x

CY7C1383D-100BZXC
1.4mm 3 Chip Enables and JTAG

Notes Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. DQs are in high-Z when exiting ZZ sleep mode.

Page 25 of 29

CY7C1381D CY7C1383D
Ordering Information continued

Speed MHz
Ordering Code
100 CY7C1381D-100AXI

CY7C1383D-100AXI

CY7C1381D-100BGI

CY7C1383D-100BGI

CY7C1381D-100BZI

CY7C1383D-100BZI

CY7C1381D-100BGXI

CY7C1383D-100BGXI

CY7C1381D-100BZXI

CY7C1383D-100BZXI

Package Name

Part and Package Type

A101 Lead-Free 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables

BG119 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG

BB165D 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.4mm 3 Chip Enables and JTAG

BG119 Lead-Free 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG

BB165D Lead-Free 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.4mm 3 Chip Enables and JTAG
Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Lead-free BG packages ordering Code:BGX will be available in

Package Diagrams
100-Pin Thin Plastic Quad Flatpack 14 x 20 x mm A101

Operating Range

Industrial
100 1
81 80

DIMENSIONS ARE IN MILLIMETERS.

R MIN. MAX.

GAUGE PLANE
0° -7°

REF.
30 31
0° MIN.

R MIN. MAX.

MIN.

DETAIL A

TYP.
51 50

STAND-OFF MIN. MAX.
12° ±1° 8X

SEATING PLANE

SEE DETAIL

MAX. MAX.
51-85050-*A

Page 26 of 29

Package Diagrams continued
119-Lead PBGA 14 x 22 x mm BG119

CY7C1381D CY7C1383D
51-85115-*B

Page 27 of 29

Package Diagrams continued
165 FBGA 13 x 15 x MM BB165D

CY7C1381D CY7C1383D
51-85180-**
i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.

Page 28 of 29

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CY7C1381D CY7C1383D

Document History Page

Document Title CY7C1381D/CY7C1383D 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM Document Number 38-05544
Added comment of ‘Lead-free BG packages availability’ below the Ordering

Information

Page 29 of 29

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Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1381D-133BGXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1381D-133BGXC 508005