CY7C1380F-167BGC

CY7C1380F-167BGC Datasheet

CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F

Part	Datasheet
CY7C1380F-167BGC	CY7C1380F-167BGC (pdf)

Related Parts	Information
CY7C1380F-167BGCT	CY7C1380F-167BGCT
CY7C1380D-167BZCT	CY7C1380D-167BZCT
CY7C1380D-167BZC	CY7C1380D-167BZC

PDF Datasheet Preview
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 18-Mbit 512K x 36/1M x 18 Pipelined SRAM Functional Description • Supports bus operation up to 250 MHz • Available speed grades are 250, 200, and 167 MHz • Registered inputs and outputs for pipelined operation • 3.3V core power supply • 2.5V or 3.3V I/O power supply • Fast clock-to-output times ns for 250 MHz device • Provides high performance 3-1-1-1 access rate • User selectable burst counter supporting Intel inter- leaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed write • Asynchronous output enable • Single cycle chip deselect • CY7C1380D/CY7C1382D is available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA package CY7C1380F/CY7C1382F is available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 119-ball BGA and 165-ball FBGA package • IEEE JTAG-Compatible Boundary Scan • ZZ sleep mode option The SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable CE1 , depth-expansion chip enables CE2 and CE3 [2] , burst control inputs ADSC, ADSP, and ADV , write enables BWX, and BWE , and global write GW . Asynchronous inputs include the output enable OE and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when address strobe processor ADSP or address strobe controller ADSC are active. Subsequent burst addresses can be internally generated as they are controlled by the advance pin ADV . Address, data inputs, and write controls are registered on-chip to initiate a self-timed write cycle.This part supports byte write operations see Table 1 on page 6 and “Truth Table” on page 10 for further details . Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F operates from a +3.3V core power supply while all outputs operate with a or +3.3V power supply. All inputs and outputs are JEDEC-standard and JESD8-5-compatible. Selection Guide Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 250 MHz 200 MHz 167 MHz Unit Notes For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on CE3, CE2 are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable. • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Logic Block Diagram CY7C1380D/CY7C1380F [3] 512K x 36 A0, A1, A MODE ADV CLK ADSC ADSP BW A BWE GW CE 1 CE 2 CE 3 OE ADDRESS REGISTER A [1:0] BURST COUNTER CLR AND Q0 Ordering Information The following table lists all speed, package and temperature range options. Please note that some options listed below may not be available for order entry. To verify the availability of a specific option, visit the Cypress website at and refer to the product summary page at or contact your local sales representative for the status of availability of parts. Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at Speed MHz Ordering Code 250 CY7C1380D-250AXC CY7C1382D-250AXC CY7C1380F-250AXC CY7C1382F-250AXC CY7C1380F-250BGC CY7C1382F-250BGC CY7C1380F-250BGXC CY7C1382F-250BGXC CY7C1380D-250BZC CY7C1382D-250BZC CY7C1380F-250BZC CY7C1382F-250BZC CY7C1380D-250BZXC CY7C1382D-250BZXC CY7C1380F-250BZXC CY7C1382F-250BZXC CY7C1380D-250AXI CY7C1382D-250AXI CY7C1380F-250AXI CY7C1382F-250AXI CY7C1380F-250BGI CY7C1382F-250BGI CY7C1380F-250BGXI CY7C1382F-250BGXI CY7C1380D-250BZI CY7C1382D-250BZI CY7C1380F-250BZI CY7C1382F-250BZI CY7C1380D-250BZXI CY7C1382D-250BZXI CY7C1380F-250BZXI CY7C1382F-250BZXI Package Diagram 51-85050 51-85115 51-85115 51-85180 51-85180 51-85050 51-85115 51-85115 51-85180 51-85180 Part and Package Type 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free 119-ball Grid Array 14 x 22 x mm 119-ball Grid Array 14 x 22 x mm Pb-Free 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm Ordering Code 200 CY7C1380D-200AXC CY7C1382D-200AXC CY7C1380F-200AXC CY7C1382F-200AXC CY7C1380F-200BGC CY7C1382F-200BGC CY7C1380F-200BGXC CY7C1382F-200BGXC CY7C1380D-200BZC CY7C1382D-200BZC CY7C1380F-200BZC CY7C1382F-200BZC CY7C1380D-200BZXC CY7C1382D-200BZXC CY7C1380F-200BZXC CY7C1382F-200BZXC CY7C1380D-200AXI CY7C1382D-200AXI CY7C1380F-200AXI CY7C1382F-200AXI CY7C1380F-200BGI CY7C1382F-200BGI CY7C1380F-200BGXI CY7C1382F-200BGXI CY7C1380D-200BZI CY7C1382D-200BZI CY7C1380F-200BZI CY7C1382F-200BZI CY7C1380D-200BZXI CY7C1382D-200BZXI CY7C1380F-200BZXI CY7C1382F-200BZXI Package Diagram 51-85050 51-85115 51-85115 51-85180 51-85180 51-85050 51-85115 51-85115 51-85180 51-85180 Part and Package Type 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free 119-ball Grid Array 14 x 22 x mm 119-ball Grid Array 14 x 22 x mm Pb-Free 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm Ordering Code 167 CY7C1380D-167AXC CY7C1382D-167AXC CY7C1380F-167AXC CY7C1382F-167AXC CY7C1380F-167BGC CY7C1382F-167BGC CY7C1380F-167BGXC CY7C1382F-167BGXC CY7C1380D-167BZC CY7C1382D-167BZC CY7C1380F-167BZC CY7C1382F-167BZC CY7C1380D-167BZXC CY7C1382D-167BZXC CY7C1380F-167BZXC CY7C1382F-167BZXC CY7C1380D-167AXI CY7C1382D-167AXI CY7C1380F-167AXI CY7C1382F-167AXI CY7C1380F-167BGI CY7C1382F-167BGI CY7C1380F-167BGXI CY7C1382F-167BGXI CY7C1380D-167BZI CY7C1382D-167BZI CY7C1380F-167BZI CY7C1382F-167BZI CY7C1380D-167BZXI CY7C1382D-167BZXI CY7C1380F-167BZXI CY7C1382F-167BZXI Package Diagram 51-85050 51-85115 51-85115 51-85180 51-85180 51-85050 51-85115 51-85115 51-85180 51-85180 Part and Package Type 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free 119-ball Grid Array 14 x 22 x mm 119-ball Grid Array 14 x 22 x mm Pb-Free 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm SYT Edited description under “IEEE Serial Boundary Scan JTAG ” for non-compliance with Removed 225MHz and 133 MHz Speed Bins Added Pb-free information for 100-Pin TQFP, 119 BGA and 165 FBGA Packages Added comment of ‘Pb-free BG packages availability’ below the Ordering Information B 326078 See ECN PCI Address expansion pins/balls in the pinouts for all packages are modified as per JEDEC standard Added description on EXTEST Output Bus Tri-State Changed description on the Tap Instruction Set Overview and Extest Changed Device Width 23:18 for 119-BGA from to 101000 Added separate row for 165 -FBGA Device Width 23:18 Changed ΘJA and ΘJC for TQFP Package from 31 and 6 °C/W to and °C/W respectively Changed ΘJA and ΘJC for BGA Package from 45 and 7 °C/W to and °C/W respectively Changed ΘJA and ΘJC for FBGA Package from 46 and 3 °C/W to and °C/W respectively Modified VOL, VOH test conditions Removed comment of ‘Pb-free BG packages availability’ below the Ordering Information Updated Ordering Information Table C 416321 See ECN Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed the description of IX from Input Load Current to Input Leakage Current on page# 18 Changed the IX current values of MODE on page # 18 from uA and 30 uA to uA and 5 uA Changed the IX current values of ZZ on page # 18 from uA and 5 uA to uA and 30 uA Changed VIH < VDD to VIH < VDDon page # 18 Replaced Package Name column with Package Diagram in the Ordering Information table Updated Ordering Information Table D 475009 See ECN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table. Updated the Ordering Information table. E 776456 See ECN Added Part numbers CY7C1380F and CY7C1382F and its related information Added footnote# 3 regarding Chip Enable Updated Ordering Information table *F 2648065 01/27/09 VKN/PYRS Modified note on top of the Ordering information table Updated Ordering Information table to include CY7C1380F/CY7C1382F in 100-Pin TSOP and 165 BGA package Page 33 of 34 [+] Feedback CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General psoc.cypress.com/solutions Low Power/Low Voltage psoc.cypress.com/low-power Precision Analog psoc.cypress.com/precision-analog LCD Drive psoc.cypress.com/lcd-drive CAN 2.0b psoc.cypress.com/can psoc.cypress.com/usb Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 34 of 34 [+] Feedback

PDF Datasheet Preview

CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F
18-Mbit 512K x 36/1M x 18 Pipelined SRAM

Functional Description
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200, and 167 MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply
• 2.5V or 3.3V I/O power supply
• Fast clock-to-output times ns for 250 MHz device
• Provides high performance 3-1-1-1 access rate
• User selectable burst counter supporting Intel inter-
leaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Single cycle chip deselect
• CY7C1380D/CY7C1382D is available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA package CY7C1380F/CY7C1382F is available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 119-ball BGA and 165-ball FBGA package
• IEEE JTAG-Compatible Boundary Scan
• ZZ sleep mode option

The SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable CE1 , depth-expansion chip enables CE2 and CE3 [2] , burst control inputs ADSC, ADSP, and ADV , write enables BWX, and BWE , and global write GW . Asynchronous inputs include the output enable OE and the ZZ pin.

Addresses and chip enables are registered at rising edge of clock when address strobe processor ADSP or address strobe controller ADSC are active. Subsequent burst addresses can be internally generated as they are controlled by the advance pin ADV .

Address, data inputs, and write controls are registered on-chip to initiate a self-timed write cycle.This part supports byte write operations see Table 1 on page 6 and “Truth Table” on page 10 for further details . Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written.

CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
operates from a +3.3V core power supply while all outputs
operate with a or +3.3V power supply. All inputs and outputs
are JEDEC-standard and JESD8-5-compatible.

Selection Guide

Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current
250 MHz
200 MHz
167 MHz

Unit

Notes For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on CE3, CE2 are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F

Logic Block Diagram CY7C1380D/CY7C1380F [3] 512K x 36

A0, A1, A

MODE ADV CLK

ADSC ADSP

BW A BWE GW

CE 1 CE 2 CE 3 OE

ADDRESS REGISTER

A [1:0]

BURST COUNTER CLR AND Q0
Ordering Information

The following table lists all speed, package and temperature range options. Please note that some options listed below may not be available for order entry. To verify the availability of a specific option, visit the Cypress website at and refer to the product summary page at or contact your local sales representative for the status of availability of parts.

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at

Speed MHz
Ordering Code
250 CY7C1380D-250AXC

CY7C1382D-250AXC

CY7C1380F-250AXC

CY7C1382F-250AXC

CY7C1380F-250BGC

CY7C1382F-250BGC

CY7C1380F-250BGXC

CY7C1382F-250BGXC

CY7C1380D-250BZC

CY7C1382D-250BZC

CY7C1380F-250BZC

CY7C1382F-250BZC

CY7C1380D-250BZXC

CY7C1382D-250BZXC

CY7C1380F-250BZXC

CY7C1382F-250BZXC

CY7C1380D-250AXI

CY7C1382D-250AXI

CY7C1380F-250AXI

CY7C1382F-250AXI

CY7C1380F-250BGI

CY7C1382F-250BGI

CY7C1380F-250BGXI

CY7C1382F-250BGXI

CY7C1380D-250BZI

CY7C1382D-250BZI

CY7C1380F-250BZI

CY7C1382F-250BZI

CY7C1380D-250BZXI

CY7C1382D-250BZXI

CY7C1380F-250BZXI

CY7C1382F-250BZXI

Package Diagram 51-85050
51-85115 51-85115 51-85180
51-85180
51-85050
51-85115 51-85115 51-85180
51-85180

Part and Package Type 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free
119-ball Grid Array 14 x 22 x mm 119-ball Grid Array 14 x 22 x mm Pb-Free 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm
Ordering Code
200 CY7C1380D-200AXC

CY7C1382D-200AXC

CY7C1380F-200AXC

CY7C1382F-200AXC

CY7C1380F-200BGC

CY7C1382F-200BGC

CY7C1380F-200BGXC

CY7C1382F-200BGXC

CY7C1380D-200BZC

CY7C1382D-200BZC

CY7C1380F-200BZC

CY7C1382F-200BZC

CY7C1380D-200BZXC

CY7C1382D-200BZXC

CY7C1380F-200BZXC

CY7C1382F-200BZXC

CY7C1380D-200AXI

CY7C1382D-200AXI

CY7C1380F-200AXI

CY7C1382F-200AXI

CY7C1380F-200BGI

CY7C1382F-200BGI

CY7C1380F-200BGXI

CY7C1382F-200BGXI

CY7C1380D-200BZI

CY7C1382D-200BZI

CY7C1380F-200BZI

CY7C1382F-200BZI

CY7C1380D-200BZXI

CY7C1382D-200BZXI

CY7C1380F-200BZXI

CY7C1382F-200BZXI

Package Diagram 51-85050
51-85115 51-85115 51-85180
51-85180
51-85050
51-85115 51-85115 51-85180
51-85180

Part and Package Type 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free
119-ball Grid Array 14 x 22 x mm 119-ball Grid Array 14 x 22 x mm Pb-Free 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm
Ordering Code
167 CY7C1380D-167AXC

CY7C1382D-167AXC

CY7C1380F-167AXC

CY7C1382F-167AXC

CY7C1380F-167BGC

CY7C1382F-167BGC

CY7C1380F-167BGXC

CY7C1382F-167BGXC

CY7C1380D-167BZC

CY7C1382D-167BZC

CY7C1380F-167BZC

CY7C1382F-167BZC

CY7C1380D-167BZXC

CY7C1382D-167BZXC

CY7C1380F-167BZXC

CY7C1382F-167BZXC

CY7C1380D-167AXI

CY7C1382D-167AXI

CY7C1380F-167AXI

CY7C1382F-167AXI

CY7C1380F-167BGI

CY7C1382F-167BGI

CY7C1380F-167BGXI

CY7C1382F-167BGXI

CY7C1380D-167BZI

CY7C1382D-167BZI

CY7C1380F-167BZI

CY7C1382F-167BZI

CY7C1380D-167BZXI

CY7C1382D-167BZXI

CY7C1380F-167BZXI

CY7C1382F-167BZXI

Package Diagram 51-85050
51-85115 51-85115 51-85180
51-85180
51-85050
51-85115 51-85115 51-85180
51-85180

Part and Package Type 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free
119-ball Grid Array 14 x 22 x mm 119-ball Grid Array 14 x 22 x mm Pb-Free 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm
SYT Edited description under “IEEE Serial Boundary Scan JTAG ” for non-compliance with Removed 225MHz and 133 MHz Speed Bins Added Pb-free information for 100-Pin TQFP, 119 BGA and 165 FBGA Packages Added comment of ‘Pb-free BG packages availability’ below the Ordering Information
*B 326078 See ECN
PCI Address expansion pins/balls in the pinouts for all packages are modified as per JEDEC standard Added description on EXTEST Output Bus Tri-State Changed description on the Tap Instruction Set Overview and Extest Changed Device Width 23:18 for 119-BGA from to 101000 Added separate row for 165 -FBGA Device Width 23:18 Changed ΘJA and ΘJC for TQFP Package from 31 and 6 °C/W to and °C/W respectively Changed ΘJA and ΘJC for BGA Package from 45 and 7 °C/W to and °C/W respectively Changed ΘJA and ΘJC for FBGA Package from 46 and 3 °C/W to and °C/W respectively Modified VOL, VOH test conditions Removed comment of ‘Pb-free BG packages availability’ below the Ordering Information Updated Ordering Information Table
*C 416321 See ECN
Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed the description of IX from Input Load Current to Input Leakage Current on page# 18 Changed the IX current values of MODE on page # 18 from uA and 30 uA to uA and 5 uA Changed the IX current values of ZZ on page # 18 from uA and 5 uA to uA and 30 uA Changed VIH < VDD to VIH < VDDon page # 18 Replaced Package Name column with Package Diagram in the Ordering Information table Updated Ordering Information Table
*D 475009 See ECN
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table. Updated the Ordering Information table.
*E 776456 See ECN
Added Part numbers CY7C1380F and CY7C1382F and its related information Added footnote# 3 regarding Chip Enable Updated Ordering Information table
*F 2648065 01/27/09 VKN/PYRS Modified note on top of the Ordering information table Updated Ordering Information table to include CY7C1380F/CY7C1382F in 100-Pin TSOP and 165 BGA package

Page 33 of 34 [+] Feedback

CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products PSoC Clocks & Buffers Wireless Memories Image Sensors
psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com

PSoC Solutions

General
psoc.cypress.com/solutions

Low Power/Low Voltage
psoc.cypress.com/low-power

Precision Analog
psoc.cypress.com/precision-analog

LCD Drive
psoc.cypress.com/lcd-drive

CAN 2.0b
psoc.cypress.com/can
psoc.cypress.com/usb

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

All products and company names mentioned in this document may be the trademarks of their respective holders.

Page 34 of 34
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1380F-167BGC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1380F-167BGC 508001