CY7C1371C-100AC
CY7C1371C-100AC Datasheet
CY7C1371C CY7C1373C
| Part | Datasheet |
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CY7C1371C-100AC |
CY7C1371C-100AC (pdf) |
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| CY7C1371C CY7C1373C 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] • No Bus Latency NoBL architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero wait states Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation • Byte Write capability • 3.3V/2.5V I/O power supply • Fast clock-to-output times ns for 133-MHz device ns for 117-MHz device ns for 100-MHz device • Clock Enable CEN pin to enable clock and suspend operation • Synchronous self-timed writes • Asynchronous Output Enable • Offered in JEDEC-standard 100 TQFP, 119-Ball BGA and 165-Ball fBGA packages • Three chip enables for simple depth expansion • Automatic Power-down feature available using ZZ mode or CE deselect • JTAG boundary scan for BGA and fBGA packages • Burst or interleaved burst order • Low standby power The CY7C1371C/CY7C1373C is a 3.3V, 512K x 36/ 1M x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371C/ CY7C1373C is equipped with the advanced No Bus Latency NoBL logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is ns 133-MHz device . Write operations are controlled by the two or four Byte Write Select BWX and a Write Enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. Selection Guide 133 MHz 117 MHz 100 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Notes For recommendations, please refer to the Cypress application note System Design Guidelines on Unit ns mA Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Logic Block Diagram CY7C1371C 512K x 36 A0, A1, A MODE ADDRESS REGISTER A1 A0 D1 D0 ADV/LD C WRITE ADDRESS REGISTER Q1 A1' Q0 A0' BURST LOGIC ADV/LD BWA BWB BWC BWD WE WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC MEMORY WRITE ARRAY DRIVERS OE CE1 READ LOGIC Ordering Information Speed MHz Ordering Code Package Name Part and Package Type 133 CY7C1371C-133AC CY7C1373C-133AC A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables CY7C1371C-133AI CY7C1373C-133AI A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables CY7C1371C-133BGC CY7C1373C-133BGC BG119 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG CY7C1371C-133BGI CY7C1373C-133BGI BG119 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG CY7C1371C-133BZC CY7C1373C-133BZC BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables and JTAG CY7C1371C-133BZI CY7C1373C-133BZI BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables and JTAG 117 CY7C1371C-117AC CY7C1373C-117AC A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables CY7C1371C-117AI CY7C1373C-117AI A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables CY7C1371C-117BGC CY7C1373C-117BGC BG119 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG CY7C1371C-117BGI CY7C1373C-117BGI BG119 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG CY7C1371C-117BZC CY7C1373C-117BZC BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables and JTAG CY7C1371C-117BZI CY7C1373C-117BZI BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables and JTAG 100 CY7C1371C-100AC CY7C1373C-100AC A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables CY7C1371C-100AI CY7C1373C-100AI A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables CY7C1371C-100BGC CY7C1373C-100BGC BG119 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG CY7C1371C-100BGI ICY7C1373C-100BGI BG119 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG CY7C1371C-100BZC CY7C1373C-100BZC BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables and JTAG CY7C1371C-100BZI CY7C1373C-100BZI BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables and JTAG Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Operating Range VBL Update Ordering Info section unshade active part numbers. 231349 See ECN DIM Pin H2 165 fBGA changed from NC to NC/VDD. Page 33 of 33 |
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