CY7C13201KV18-333BZXC

CY7C13201KV18-333BZXC Datasheet

CY7C13201KV18

Part	Datasheet
CY7C13201KV18-333BZXC	CY7C13201KV18-333BZXC (pdf)

Related Parts	Information
CY7C13201KV18-300BZXC	CY7C13201KV18-300BZXC

PDF Datasheet Preview
CY7C13201KV18 18-Mbit DDR II SRAM 2-Word Burst Architecture • 18 Mbit Density 512K x 36 • 333 MHz Clock for High Bandwidth • 2-Word Burst to Reduce Address Bus Frequency • Double Data Rate DDR Interfaces data transferred at 666 MHz at 333 MHz • Two Input Clocks K and K for Precise DDR Timing SRAM uses rising edges only • Two Input Clocks for Output Data C and C to minimize Clock Skew and Flight Time Mismatches • Echo Clocks CQ and CQ simplify Data Capture in High Speed Systems • Synchronous Internally Self Timed Writes • DDR II Operates with Cycle Read Latency when DOFF is Asserted HIGH • Operates Similar to DDR I Device with 1 Cycle Read Latency when DOFF is Asserted LOW • 1.8V Core Power Supply with HSTL Inputs and Outputs • Variable Drive HSTL Output Buffers • Expanded HSTL Output Voltage Supports both 1.5V and 1.8V I/O supply • Available in 165-Ball FBGA Package 13 x 15 x mm • Offered in both Pb-free and Non Pb-free Packages • JTAG Compatible Test Access Port • Phase Locked Loop PLL for Accurate Data Placement Configuration CY7C13201KV18 512K x 36 Functional Description The CY7C13201KV18 is 1.8V Synchronous Pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. The burst counter takes in the least significant bit of the external address and bursts two 36-bit words sequentially into or out of the device. Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs Q, sharing the same physical pins as the data inputs D are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. Output data clocks C/C enable maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. This device is down bonded from the 65 nm 72M QDRII device and has the same IDD/ISB1 values and JTAG ID code as the equivalent 72M device option. For details refer to the application note AN53189, 65 nm Technology Interim QDRII/DDRII SRAM Device Family Description. Table Selection Guide Description Maximum Operating Frequency Maximum Operating Current 333 MHz 333 640 300 MHz 300 600 250 MHz 250 530 200 MHz 200 450 167 MHz 167 400 Unit MHz mA • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Logic Block Diagram CY7C13201KV18 CY7C13201KV18 Burst Logic A 18:0 19 18 A 18:1 Address Register K DOFF CLK Gen. VREF R/W BWS[3:0] Control Logic Write Add. Decode Read Add. Decode Write Reg Write Reg 256K x 36 Array 256K x 36 Array Ordering Information The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at Table Ordering Information Speed MHz Ordering Code 333 CY7C13201KV18-333BZXC 300 CY7C13201KV18-300BZXC Package Diagram Package Type Operating Range 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free Commercial Package Diagram Figure 165-Ball FBGA 13 x 15 x mm , 51-85180 TOP VIEW PIN 1 CORNER 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R SEATING PLANE C MAX. C BOTTOM VIEW PIN 1 CORNER M C M C A B 165X 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 0.15 4X NOTES : SOLDER PAD TYPE NON-SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.475g JEDEC REFERENCE MO-216 / ISSUE E PACKAGE CODE BB0AC 51-85180 B Page 22 of 23 [+] Feedback CY7C13201KV18 Document History Page Document Title CY7C13201KV18, 18 Mbit DDR II SRAM 2-Word Burst Architecture Document Number 001-54142 Orig. of Change Submission Date Description of Change * 2723978 VKN/AESA 06/25/09 New Data Sheet A 2747707 VKN/AESA 08/03/2009 Converted from preliminary to final Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information B 2762555 09/11/2009 Updated Input and Output Capacitance. Modified Ordering code disclaimer. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 23 of 23 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY7C13201KV18
18-Mbit DDR II SRAM 2-Word Burst Architecture
• 18 Mbit Density 512K x 36
• 333 MHz Clock for High Bandwidth
• 2-Word Burst to Reduce Address Bus Frequency
• Double Data Rate DDR Interfaces
data transferred at 666 MHz at 333 MHz
• Two Input Clocks K and K for Precise DDR Timing

SRAM uses rising edges only
• Two Input Clocks for Output Data C and C to minimize Clock

Skew and Flight Time Mismatches
• Echo Clocks CQ and CQ simplify Data Capture in High Speed

Systems
• Synchronous Internally Self Timed Writes
• DDR II Operates with Cycle Read Latency when DOFF is

Asserted HIGH
• Operates Similar to DDR I Device with 1 Cycle Read Latency
when DOFF is Asserted LOW
• 1.8V Core Power Supply with HSTL Inputs and Outputs
• Variable Drive HSTL Output Buffers
• Expanded HSTL Output Voltage

Supports both 1.5V and 1.8V I/O supply
• Available in 165-Ball FBGA Package 13 x 15 x mm
• Offered in both Pb-free and Non Pb-free Packages
• JTAG Compatible Test Access Port
• Phase Locked Loop PLL for Accurate Data Placement

Configuration

CY7C13201KV18 512K x 36

Functional Description

The CY7C13201KV18 is 1.8V Synchronous Pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. The burst counter takes in the least significant bit of the external address and bursts two 36-bit words sequentially into or out of the device.

Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs Q, sharing the same physical pins as the data inputs D are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. Output data clocks C/C enable maximum system clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

This device is down bonded from the 65 nm 72M QDRII device and has the same IDD/ISB1 values and JTAG ID code as the equivalent 72M device option. For details refer to the application note AN53189, 65 nm Technology Interim QDRII/DDRII SRAM Device Family Description.

Table Selection Guide Description

Maximum Operating Frequency Maximum Operating Current
333 MHz 333 640
300 MHz 300 600
250 MHz 250 530
200 MHz 200 450
167 MHz 167 400

Unit MHz mA
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Logic Block Diagram CY7C13201KV18

CY7C13201KV18

Burst

Logic

A 18:0 19 18 A 18:1

Address Register

K DOFF

CLK Gen.

VREF R/W BWS[3:0]

Control Logic

Write Add. Decode Read Add. Decode

Write Reg

Write Reg
256K x 36 Array 256K x 36 Array
Ordering Information

The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at
Table Ordering Information

Speed MHz
Ordering Code
333 CY7C13201KV18-333BZXC
300 CY7C13201KV18-300BZXC

Package Diagram

Package Type

Operating Range
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free Commercial

Package Diagram

Figure 165-Ball FBGA 13 x 15 x mm , 51-85180

TOP VIEW

PIN 1 CORNER
1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R

SEATING PLANE C

MAX. C

BOTTOM VIEW PIN 1 CORNER

M C M C A B 165X
11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R
0.15 4X

NOTES :

SOLDER PAD TYPE NON-SOLDER MASK DEFINED NSMD

PACKAGE WEIGHT 0.475g

JEDEC REFERENCE MO-216 / ISSUE E

PACKAGE CODE BB0AC
51-85180 *B

Page 22 of 23 [+] Feedback

CY7C13201KV18

Document History Page

Document Title CY7C13201KV18, 18 Mbit DDR II SRAM 2-Word Burst Architecture Document Number 001-54142

Orig. of Change

Submission Date

Description of Change
** 2723978 VKN/AESA 06/25/09 New Data Sheet
*A 2747707 VKN/AESA 08/03/2009 Converted from preliminary to final Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information
*B 2762555
09/11/2009 Updated Input and Output Capacitance. Modified Ordering code disclaimer.

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products PSoC Clocks & Buffers Wireless Memories Image Sensors
psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 23 of 23

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.
[+] Feedback

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Datasheet ID: CY7C13201KV18-333BZXC 507963