CY7C1059DV33-10BAXI

CY7C1059DV33-10BAXI Datasheet

CY7C1059DV33

Part	Datasheet
CY7C1059DV33-10BAXI	CY7C1059DV33-10BAXI (pdf)

PDF Datasheet Preview
CY7C1059DV33 8-Mbit 1M x 8 Static RAM • High speed tAA = 10 ns • Low active power ICC = 110 mA • Low CMOS standby power ISB2 = 20 mA • 2.0V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features • Available in lead-free 36-ball FBGA and 44-pin TSOP II ZS44 packages Logic Block Diagram Functional Description[1] The CY7C1059DV33 is a high-performance CMOS Static RAM organized as 1M words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable CE , an active LOW Output Enable OE , and tri-state drivers. Writing to the device is accomplished by taking Chip Enable CE and Write Enable WE inputs LOW. Data on the eight I/O pins I/O0 through I/O7 is then written into the location specified on the address pins A0 through A19 . Reading from the device is accomplished by taking Chip Enable CE and Output Enable OE LOW while forcing Write Enable WE HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins I/O0 through I/O7 are placed in a high-impedance state when the device is deselected CE HIGH , the outputs are disabled OE HIGH , or during a Write operation CE LOW, and WE LOW . ROW DECODER A11 A12 A13 A14 A15 A16 A17 A18 SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A 10 CE WE INPUT BUFFER 1M x 8 ARRAY COLUMN DECODER POWER DOWN I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Note For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Pin Configuration 36-ball FBGA Top View 12 34 56 A0 A1 NC A3 A6 A8 I/O4 A2 WE A4 A7 I/O0 I/O5 A19 A5 I/O1 I/O6 A18 A17 I/O2 I/O7 OE CE A16 A15 I/O3 A10 A11 A12 A13 A14 CY7C1059DV33 TSOP II Top View A0 3 A1 4 A2 5 A3 6 A4 7 CE 8 I/O0 9 Ordering Information Speed ns Ordering Code CY7C1059DV33-10BAXI CY7C1059DV33-10ZSXI Package Diagram 51-85105 51-85087 Package Type 36-ball FBGA Pb-Free 44-pin TSOP II Pb-Free Please contact your local Cypress sales representative for availability of these parts. Package Diagrams 36-Ball FBGA mm x mm x mm 51-85105 CY7C1059DV33 Power Standby ISB Active ICC Active ICC Active ICC Operating Range Industrial 51-85105-D Page 7 of 9 Package Diagrams continued 44-pin TSOP II 51-85087 CY7C1059DV33 51-85087-A All product and company names mentioned in this document may be the trademarks of their respective holders. Page 8 of 9 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C1059DV33 Document History Page Document Title CY7C1059DV33 8-Mbit 1M x 8 Static RAM Document Number 001-00061 Orig. of ECN NO. Issue Date Change Description of Change 342195 See ECN PCI New Data Sheet 380574 See ECN SYT Redefined ICC values for Com’l and Ind’l temperature ranges ICC Com’l Changed from 110, 90 and 80 mA to 110, 100 and 95 mA for 8, 10 and 12 ns speed bins respectively ICC Ind’l Changed from 110, 90 and 80 mA to 120, 110 and 105 mA for 8, 10 and 12 ns speed bins respectively Changed the Capacitance values from 8 pF to 10 pF on Page # 3 485796 See ECN NXR Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Removed -8 and -12 Speed bins from product offering, Removed Commercial Operating Range option, Modified Maximum Ratings for DC input voltage from -0.5V to -0.3V and VCC + 0.5V to VCC + 0.3V Updated footnote #7 on High-Z parameter measurement Added footnote #11 Updated the Ordering Information table and Replaced Package Name column with Package Diagram. Page 9 of 9

PDF Datasheet Preview

CY7C1059DV33
8-Mbit 1M x 8 Static RAM
• High speed tAA = 10 ns
• Low active power ICC = 110 mA
• Low CMOS standby power ISB2 = 20 mA
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in lead-free 36-ball FBGA and 44-pin TSOP II

ZS44 packages

Logic Block Diagram

Functional Description[1]

The CY7C1059DV33 is a high-performance CMOS Static RAM organized as 1M words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable CE , an active LOW Output Enable OE , and tri-state drivers. Writing to the device is accomplished by taking Chip Enable CE and Write Enable WE inputs LOW. Data on the eight I/O pins I/O0 through I/O7 is then written into the location specified on the address pins A0 through A19 .

Reading from the device is accomplished by taking Chip Enable CE and Output Enable OE LOW while forcing Write Enable WE HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.

The eight input/output pins I/O0 through I/O7 are placed in a high-impedance state when the device is deselected CE HIGH , the outputs are disabled OE HIGH , or during a Write operation CE LOW, and WE LOW .

ROW DECODER

A11 A12 A13 A14 A15 A16 A17 A18

SENSE AMPS

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A 10

CE WE

INPUT BUFFER
1M x 8 ARRAY

COLUMN DECODER

POWER DOWN

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

Note For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600

Pin Configuration
36-ball FBGA Top View
12 34 56

A0 A1 NC A3 A6 A8

I/O4 A2 WE A4 A7 I/O0

I/O5

A19 A5

I/O1

I/O6

A18 A17

I/O2

I/O7 OE CE A16 A15 I/O3

A10 A11 A12 A13 A14

CY7C1059DV33

TSOP II Top View

A0 3 A1 4 A2 5 A3 6 A4 7 CE 8

I/O0 9
Ordering Information

Speed ns
Ordering Code CY7C1059DV33-10BAXI CY7C1059DV33-10ZSXI

Package Diagram
51-85105
51-85087

Package Type 36-ball FBGA Pb-Free 44-pin TSOP II Pb-Free

Please contact your local Cypress sales representative for availability of these parts.

Package Diagrams
36-Ball FBGA mm x mm x mm 51-85105

CY7C1059DV33

Power Standby ISB Active ICC Active ICC Active ICC

Operating Range

Industrial
51-85105-*D

Page 7 of 9

Package Diagrams continued
44-pin TSOP II 51-85087

CY7C1059DV33
51-85087-*A

All product and company names mentioned in this document may be the trademarks of their respective holders.

Page 8 of 9

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CY7C1059DV33

Document History Page

Document Title CY7C1059DV33 8-Mbit 1M x 8 Static RAM Document Number 001-00061

Orig. of ECN NO. Issue Date Change

Description of Change
342195 See ECN

PCI New Data Sheet
380574 See ECN

SYT Redefined ICC values for Com’l and Ind’l temperature ranges

ICC Com’l Changed from 110, 90 and 80 mA to 110, 100 and 95 mA for 8,
10 and 12 ns speed bins respectively

ICC Ind’l Changed from 110, 90 and 80 mA to 120, 110 and 105 mA for 8, 10 and 12 ns speed bins respectively

Changed the Capacitance values from 8 pF to 10 pF on Page # 3
485796 See ECN NXR Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”

Removed -8 and -12 Speed bins from product offering,

Removed Commercial Operating Range option,

Modified Maximum Ratings for DC input voltage from -0.5V to -0.3V and

VCC + 0.5V to VCC + 0.3V Updated footnote #7 on High-Z parameter measurement

Added footnote #11
Updated the Ordering Information table and Replaced Package Name column
with Package Diagram.

Page 9 of 9

More datasheets: A2557EB | CC65-110 | ALMD-CM3D-Y1002 | 100LVEL11M | 100LVEL11MX | 2342 | 1361E514 | 1362E514 | FDB2670 | FDP2670

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1059DV33-10BAXI Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1059DV33-10BAXI 507909