CY7C1020CV33-10ZXC

CY7C1020CV33-10ZXC Datasheet

CY7C1020CV33

Part	Datasheet
CY7C1020CV33-10ZXC	CY7C1020CV33-10ZXC (pdf)

Related Parts	Information
CY7C1020CV33-10ZXCT	CY7C1020CV33-10ZXCT
CY7C1020CV33-15ZC	CY7C1020CV33-15ZC

PDF Datasheet Preview
CY7C1020CV33 512K 32K x 16 Static RAM • Pin- and function-compatible with CY7C1020V33 • Temperature Ranges Commercial 0°C to 70°C Industrial to 85°C Automotive to 125°C • High speed tAA = 10 ns • CMOS for optimum speed/power • Low active power 325 mW max. • Automatic power-down when deselected • Independent control of upper and lower bits • Available in Pb-free and non Pb-free 44-pin TSOP II package ROW DECODER A8 A9 A10 A11 A12 A13 A14 SENSE AMPS Logic Block Diagram DATA IN DRIVERS 32K x 16 RAM Array COLUMN DECODER Note NC pins are not connected on the die Functional Description The CY7C1020CV33 is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable CE and Write Enable WE inputs LOW. If Byte Low Enable BLE is LOW, then data from I/O pins I/O1 through I/O8 , is written into the location specified on the address pins A0 through A14 . If Byte High Enable BHE is LOW, then data from I/O pins I/O9 through I/O16 is written into the location specified on the address pins A0 through A14 . Reading from the device is accomplished by taking Chip Enable CE and Output Enable OE LOW while forcing the Write Enable WE HIGH. If Byte Low Enable BLE is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable BHE is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins I/O1 through I/O16 are placed in a high-impedance state when the device is deselected CE HIGH , the outputs are disabled OE HIGH , the BHE and BLE are disabled BHE, BLE HIGH , or during a write operation CE LOW, and WE LOW . The CY7C1020CV33 is available in standard 44-pin TSOP Type II package. BHE WE CE OE BLE PinConfiguration[1] TSOP II Top View A3 2 A2 3 A1 4 A0 5 CE 6 I/O1 7 I/O2 8 I/O3 9 I/O4 10 VCC 11 VSS 12 I/O5 13 I/O6 14 I/O7 15 I/O8 16 WE 17 A4 18 A14 19 A13 20 A12 21 NC 22 44 A5 43 A6 42 A7 41 OE 40 BHE 39 BLE 38 I/O16 37 I/O15 36 I/O14 35 I/O13 34 VSS 33 VCC 32 I/O12 31 I/O11 30 I/O10 29 I/O9 28 NC 27 A8 26 A9 25 A10 24 A11 23 NC Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C1020CV33 Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Com’l/Ind’l Automotive Com’l/Ind’l Automotive Unit Pin Definitions Pin Name Ordering Information Speed ns 10 12 15 Ordering Code CY7C1020CV33-10ZC CY7C1020CV33-10ZXC CY7C1020CV33-12ZC CY7C1020CV33-15ZC CY7C1020CV33-15ZE CY7C1020CV33-15ZSXE Package Diagram 51-85087 Package Type 44-pin TSOP Type II 44-pin TSOP Type II Pb-Free 44-pin TSOP Type II 44-pin TSOP Type II 44-pin TSOP Type II 44-pin TSOP Type II Pb-Free Power Standby ISB Active ICC Active ICC Active ICC Active ICC Active ICC Active ICC Active ICC Active ICC Operating Range Commercial Commercial Automotive Page 7 of 9 [+] Feedback Package Diagrams 44-Pin TSOP II 51-85087 PIN 1 I.D. 1 CY7C1020CV33 DIMENSION IN MM INCH MAX MIN. TOP VIEW BOTTOM VIEW OR E KXA EJECTOR PIN BASE PLANE SEATING PLANE 0° -5° 51-85087-*A All products and company names mentioned in this document may be the trademarks of their respective holders. Page 8 of 9 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1020CV33 Document History Page Document Title CY7C1020CV33 512K 32K x 16 Static RAM Document Number 38-05133 Orig. of ECN NO. Issue Date Change Description of Change 109428 12/16/01 HGK New Data Sheet 115045 05/30/02 HGK ICC and ISB1 data modified 117615 08/14/02 DFP Pin 1= NC Pin 18 = A4 remove SOJ package option remove 8ns option. Removed IOS parameter from DC Electrical Characteristics table Updated Ordering Information Table Page 9 of 9 [+] Feedback

PDF Datasheet Preview

CY7C1020CV33
512K 32K x 16 Static RAM
• Pin- and function-compatible with CY7C1020V33
• Temperature Ranges

Commercial 0°C to 70°C Industrial to 85°C Automotive to 125°C
• High speed tAA = 10 ns
• CMOS for optimum speed/power
• Low active power 325 mW max.
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in Pb-free and non Pb-free 44-pin TSOP II package

ROW DECODER A8 A9 A10 A11 A12 A13 A14

SENSE AMPS

Logic Block Diagram

DATA IN DRIVERS
32K x 16

RAM Array

COLUMN DECODER

Note NC pins are not connected on the die

Functional Description

The CY7C1020CV33 is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected.

Writing to the device is accomplished by taking Chip Enable CE and Write Enable WE inputs LOW. If Byte Low Enable BLE is LOW, then data from I/O pins I/O1 through I/O8 , is written into the location specified on the address pins A0 through A14 . If Byte High Enable BHE is LOW, then data from I/O pins I/O9 through I/O16 is written into the location specified on the address pins A0 through A14 .

Reading from the device is accomplished by taking Chip Enable CE and Output Enable OE LOW while forcing the Write Enable WE HIGH. If Byte Low Enable BLE is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable BHE is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes.

The input/output pins I/O1 through I/O16 are placed in a high-impedance state when the device is deselected CE HIGH , the outputs are disabled OE HIGH , the BHE and BLE are disabled BHE, BLE HIGH , or during a write operation CE LOW, and WE LOW .

The CY7C1020CV33 is available in standard 44-pin TSOP Type II package.

BHE WE CE OE BLE

PinConfiguration[1]

TSOP II Top View

A3 2 A2 3 A1 4 A0 5 CE 6 I/O1 7 I/O2 8 I/O3 9

I/O4 10 VCC 11 VSS 12 I/O5 13 I/O6 14 I/O7 15 I/O8 16 WE 17

A4 18

A14 19 A13 20 A12 21 NC 22
44 A5 43 A6
42 A7 41 OE
40 BHE 39 BLE
38 I/O16 37 I/O15 36 I/O14 35 I/O13 34 VSS 33 VCC 32 I/O12 31 I/O11 30 I/O10 29 I/O9 28 NC 27 A8 26 A9 25 A10 24 A11 23 NC

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C1020CV33

Selection Guide

Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current

Com’l/Ind’l

Automotive

Com’l/Ind’l

Automotive

Unit

Pin Definitions

Pin Name
Ordering Information

Speed ns 10
12 15
Ordering Code CY7C1020CV33-10ZC CY7C1020CV33-10ZXC CY7C1020CV33-12ZC CY7C1020CV33-15ZC CY7C1020CV33-15ZE CY7C1020CV33-15ZSXE

Package Diagram
51-85087

Package Type 44-pin TSOP Type II 44-pin TSOP Type II Pb-Free 44-pin TSOP Type II 44-pin TSOP Type II 44-pin TSOP Type II 44-pin TSOP Type II Pb-Free

Power Standby ISB Active ICC Active ICC Active ICC Active ICC Active ICC Active ICC Active ICC Active ICC

Operating Range

Commercial

Commercial Automotive

Page 7 of 9 [+] Feedback

Package Diagrams
44-Pin TSOP II 51-85087

PIN 1 I.D. 1

CY7C1020CV33

DIMENSION IN MM INCH MAX MIN.

TOP VIEW

BOTTOM VIEW

OR E KXA

EJECTOR PIN

BASE PLANE

SEATING PLANE
0° -5°
51-85087-*A

All products and company names mentioned in this document may be the trademarks of their respective holders.

Page 8 of 9

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback

CY7C1020CV33

Document History Page

Document Title CY7C1020CV33 512K 32K x 16 Static RAM Document Number 38-05133

Orig. of ECN NO. Issue Date Change

Description of Change
109428 12/16/01

HGK New Data Sheet
115045 05/30/02

HGK ICC and ISB1 data modified
117615 08/14/02

DFP Pin 1= NC Pin 18 = A4 remove SOJ package option remove 8ns option.
Removed IOS parameter from DC Electrical Characteristics table Updated Ordering Information Table

Page 9 of 9 [+] Feedback

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Datasheet ID: CY7C1020CV33-10ZXC 507887