CY7C09449PV-AC

CY7C09449PV-AC Datasheet

CY7C09449PV-AC

Part	Datasheet
CY7C09449PV-AC	CY7C09449PV-AC (pdf)

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09449PV CY7C09449PV-AC 128 Kb Dual-Port SRAM with PCI Bus Controller PCI-DP • 128 Kb of dual-ported shared memory • Master and Target PCI Specification compliant in- terface • Embedded host bridge capability • Direct interface to many microprocessors • I2O message transport unit includes four 32-bit, 32- entry FIFO • Local bus clock rates up to 50 MHz • Single 3.3V Power Supply including compatibility with 3V and 5V PCI Bus signaling • 160-pin thin plastic quad flat package Introduction The CY7C09449PV is one of the PCI interface controllers in the Cypress Semiconductor PCI-DP family. The CY7C09449PV provides a PCI master/target interface with direct connections to many popular microprocessors. It provides 128 Kb of dual-port SRAM that is used as shared memory between the local microprocessor and the PCI bus. An I2O message unit, complete with message queues and interrupt capability, is also provided. The CY7C09449PV allows the designer to interface an application to the PCI bus in a straightforward, inexpensive way. Functional Overview A primary resource within the CY7C09449PV is its 128 Kb of dual-port memory. This memory is interfaced to both the PCI bus and to a local microprocessor bus. This shared memory can be accessed as a target from both buses at the same time for inter-process communication. From either the local or PCI bus the CY7C09449PV can be directed to become a PCI bus master to move data into or out of the internal shared memory as a direct memory access DMA . The CY7C09449PV can DMA across the PCI bus any number of 32-bit double words DWORD , up to 16K bytes. It uses the full bursting capabilities of the PCI bus for maximum efficiency and can transfer data over the full 32-bit PCI address space. The CY7C09449PV implements optional requirements of the PCI specification by selecting the optimum PCI command for each transaction it masters to the PCI bus. This maximizes overall efficiency of the system platform. PCI bridging functions PCI-to-PCI and Host-to-PCI bridges use the commands to enhance prefetch and cache coherency operations. The CY7C09449PV requests and gains access to the PCI bus as any master. It does not, within itself, include a PCI bus arbitration function. Standard PC PCI buses include this function embedded systems may need to implement this function. The CY7C09449PV provides a direct access mechanism from the local bus to the PCI bus. With it, the local processor can direct the CY7C09449PV to run a PCI bus master cycle of any kind to any address. This means that the CY7C09449PV can run PCI configuration cycles allowing it to be used as a host bridge. The CY7C09449PV is composed of a number of shared resources that allow effective data movement between the local bus and the PCI bus. Table of Contents Introduction Functional Overview Pin Configuration Pin Description PCI Bus Local Bus Timing Diagrams I2C Serial Port and Auto-Configuration Operations Registers Performance Characteristics CY7C09449PV Operations Ordering Information Package Diagram Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 CY7C09449PV-AC Bus Master/Slave Interface Up to 16 KByte Burst Transfers on PCI Bus User-Configurable Target Interfac Supports Burst Mode PCI Bus PCI Bus Interface Local Processor Bus Interface 128 Kb Dual-Port Shared Memory I2O Message Transport Unit Operations Registers Local Bus I2C SCL/SDA PCI-DPTM Allows Local Processor Provides Required FIFOs and Direct Access to PCI Bus Interrupt Status Registers AN3042_BD.vs Four First-In First-Out FIFO storage elements provide another resource to the user. These are accessible from either the PCI bus or the Local bus. When the I2O messaging unit functionality of the CY7C09449PV is to be used, the four FIFOs become part of the I2O messaging unit of the CY7C09449PV. The I2O messaging unit consists of the four FIFOs and the I2O system interrupt registers. The shared memory of the CY7C09449PV may be used to store I2O message frame buffers while most of shared memory is still available for generals purpose use. Efficient I2O messaging is realized when the local processor uses the CY7C09449PV direct access mechanism. It can be used to retrieve and post I2O message pointers to other I2O agents. Data transfer of the messages themselves is made very efficient using the CY7C09449PV PCI DMA controller to burst the message frames to other I2O agents. Interprocess communication is supported by two resources of the CY7C09449PV the mailbox registers and the arbitration flags. By writing to the mailbox registers, a method is available for the local processor to pass data while causing an interrupt to the host, and vice versa. This is enabled by the interrupt mask located in the CY7C09449PV Operations Registers. The arbitration flags are four pairs of bits that can be used to manage resource allocation and sharing between software and system processes. The CY7C09449PV includes an interrupt controller. There are separate interrupt mask and command/status registers for the PCI bus and the Local bus. The interrupt sources are DMA completion, mailbox, FIFO not empty also for I2O , FIFO overflow, PCI master abort, PCI target abort, and there is an external interrupt input pin. This interrupt controller is used to signal interrupts onto the PCI bus and the Local bus. The CY7C09449PV interrupt controller does not perform the interrupt controller function for the PCI bus system. Standard PC PCI systems include this function embedded systems may need to implement this function. An I2C-compatible serial interface is provided to allow the use of a serial EEPROM for non-volatile storage of CY7C09449PV initialization parameters. The parameters are PCI configuration and local bus settings. The CY7C09449PV will optionally access the EEPROM after reset and download initialization information before responding to PCI or local bus transactions. A wide variety of available I2C-compatible serial components are available to the local and host processor when connected through this interface. The CY7C09449PV local bus is a flexible, configurable interface that is designed to readily connect to many industry standard microprocessors. In most cases, no external interface logic “glue” is needed. The following block diagram illustrates a generic application for the CY7C09449PV. Page 2 of 50 PCI System Bus Processor Local Bus CY7C09449PV-AC PCI Add-In Card or PCI System Host CY7C09449PV 128K Bit Shared Memory Processor Power QUICC, 80x86, DSP, etc. Memory SRAM, DRAM, FLASH, etc. Peripherals Mass Storage, ATM, Special, etc. 3042APP.VSD DB 6/02 Page 3 of 50 Pin Configuration ADR[9] VSS12 VDD1 ADR[8] ADR[7] ADR[6] 14 BURST_STYLE Defines the data ordering protocol of bursts on the local bus. 0 = normal linear bursts default 1 = 486 style burst byte ordering in a burst is 048C 40C8 8C04 C840 13 INT_POL Defines the polarity of the IRQ_OUT output signal. 0 = Active LOW interrupt to the local processor default 1 = Active HIGH interrupt to the local processor 12 BLAST_POL Defines the polarity of the BLAST input signal. 0 = Active LOW default 1 = Active HIGH 11 ALE_POL Defines the polarity of the ALE input signal. 0 = Active LOW1 = Active HIGH default 10 RDYOUT_POL Defines the polarity of the RDY_OUT output signal. 0 = Active LOW default 1 = Active HIGH 9:8 BW Defines the data bus width of the local processor interface. 00 = 8 bit10 = 32 bit 01 = 16 bit11 = 32 bit with encoded byte enables per Motorola protocol default 7 BLASTMODE Determines the function of the BLAST input signal. 0 = BLAST is active only during the last transaction of the burst default 1 = BLAST is active throughout the entire burst, and goes inactive when with RDY_IN or RDY_IN become inactive on the last read or write of the burst. -- DO NOT set BLASTMODE = 1 when XTND_RDY_OUT = 6 BEMODE Determines the byte enable encoding for 16 and 32 bit Motorola modes. 0 = normal byte enables1 = Motorola byte enable encoding. default Page 39 of 50 CY7C09449PV-AC 5:4 RWMODE Defines how the READ, WRITE, and address STROBE input signals are interpreted internally and defines the Internal Address Strobe. The active polarity of STROBE is determined by ASMODE. ‘01’ is default. Pin Name RWMODE = 00 RWMODE = 01 RWMODE = 1X READ Not Used READ data used as Internal Strobe WRITE Not Used WRITE data used as Internal Strobe STROBE Internal Address Strobe Internal Address Strobe Not used as Internal Address Strobe 3:2 ASMODE Bit 2 defines the polarity of STROBE input signal. And bit 3 defines the edge of CLKIN used to sample the Internal Address Strobe see field RWMODE for a defining characteristic of the Internal Address Strobe x0 = STROBE is active LOW default x1 = STROBE is active HIGH 0x = Internal Address Strobe rising edge sampled default 1x = Internal Address Strobe falling edge sampled 1 DDIN Delayed Data Input -- Defines protocol for validated input data. 0 = input data is valid during the current cycle when RDY_IN, RDY_IN, and RDY_OUT are active. default 1 = input data is valid one cycle after when RDY_IN, RDY_IN, and RDY_OUT are active. 0 DDOUT Delayed Data Output -- Defines protocol for validated output data. 0 = output data is valid during current cycle when RDY_IN, RDY_IN, and RDY_OUT are active. default 1 = output data is valid one cycle after when RDY_IN, RDY_IN, and RDY_OUT are active. Page 40 of 50 CY7C09449PV-AC Performance Characteristics Absolute Maximum Ratings [4] Storage Temperature to +125°C Ambient Temperature Under Bias................. to +85°C Max Operating Current IDD [5,6] mA Voltage on Any VDD Pin Referenced to VSS to +4.0V Voltage on Any Signal Pin Referenced to +7.0V Recommended Operating Environment Ambient Operating Temperature................... TA0°C to +70°C Supply Voltage to +3.6V Ground Voltage Reference FCLK PCI Clock Input Frequency ...... CLK0 MHz to 33 MHz FCLKIN Local Bus Clock Input Ordering Information Ordering Code CY7C09449PV-AC Package Name Package Type TQFP160 160-Pin Plastic Thin Quad Flat Pack Operating Range 0°C to +70°C Package Diagram Pin 1 Pin 160 Page 48 of 50 Package Diagram continued CY7C09449PV-AC Page 49 of 50 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C09449PV-AC Document Title CY7C09449PV-AC 128Kb Dual-Port SRAM with PCI Bus Controller PCI-DP Document Number 38-06061 ECN NO. Issue Date Orig. of Change Description of Change 113168 02/14/02 DSG Change from Spec number 38-01014 to 38-05172 Change from Spec number 38-05172 to 38-06061 122309 12/27/02 RBI Power up requirements added to Absolute Maximum Ratings Information Page 50 of 50

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09449PV

CY7C09449PV-AC
128 Kb Dual-Port SRAM with PCI Bus Controller PCI-DP
• 128 Kb of dual-ported shared memory
• Master and Target PCI Specification compliant in-
terface
• Embedded host bridge capability
• Direct interface to many microprocessors
• I2O message transport unit includes four 32-bit, 32-
entry FIFO
• Local bus clock rates up to 50 MHz
• Single 3.3V Power Supply including compatibility with
3V and 5V PCI Bus signaling
• 160-pin thin plastic quad flat package

Introduction

The CY7C09449PV is one of the PCI interface controllers in the Cypress Semiconductor PCI-DP family. The CY7C09449PV provides a PCI master/target interface with direct connections to many popular microprocessors. It provides 128 Kb of dual-port SRAM that is used as shared memory between the local microprocessor and the PCI bus. An I2O message unit, complete with message queues and interrupt capability, is also provided. The CY7C09449PV allows the designer to interface an application to the PCI bus in a straightforward, inexpensive way.

Functional Overview

A primary resource within the CY7C09449PV is its 128 Kb of dual-port memory. This memory is interfaced to both the PCI bus and to a local microprocessor bus. This shared memory can be accessed as a target from both buses at the same time for inter-process communication. From either the local or PCI bus the CY7C09449PV can be directed to become a PCI bus master to move data into or out of the internal shared memory as a direct memory access DMA . The CY7C09449PV can DMA across the PCI bus any number of 32-bit double words DWORD , up to 16K bytes. It uses the full bursting capabilities of the PCI bus for maximum efficiency and can transfer data over the full 32-bit PCI address space.

The CY7C09449PV implements optional requirements of the PCI specification by selecting the optimum PCI command for each transaction it masters to the PCI bus. This maximizes overall efficiency of the system platform. PCI bridging functions PCI-to-PCI and Host-to-PCI bridges use the commands to enhance prefetch and cache coherency operations. The CY7C09449PV requests and gains access to the PCI bus as any master. It does not, within itself, include a PCI bus arbitration function. Standard PC PCI buses include this function embedded systems may need to implement this function.

The CY7C09449PV provides a direct access mechanism from the local bus to the PCI bus. With it, the local processor can direct the CY7C09449PV to run a PCI bus master cycle of any kind to any address. This means that the CY7C09449PV can run PCI configuration cycles allowing it to be used as a host bridge.

The CY7C09449PV is composed of a number of shared resources that allow effective data movement between the local bus and the PCI bus.

Table of Contents

Introduction

Functional Overview

Pin Configuration

Pin Description

PCI Bus

Local Bus

Timing Diagrams

I2C Serial Port and Auto-Configuration

Operations Registers

Performance Characteristics

CY7C09449PV Operations
Ordering Information

Package Diagram

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose
• CA 95134
• 408-943-2600

CY7C09449PV-AC

Bus Master/Slave Interface

Up to 16 KByte Burst Transfers on PCI Bus

User-Configurable Target Interfac Supports Burst Mode

PCI Bus

PCI Bus Interface Local Processor Bus Interface
128 Kb Dual-Port Shared Memory

I2O Message Transport Unit

Operations Registers

Local Bus I2C SCL/SDA

PCI-DPTM Allows Local Processor Provides Required FIFOs and Direct Access to PCI Bus Interrupt Status Registers AN3042_BD.vs

Four First-In First-Out FIFO storage elements provide another resource to the user. These are accessible from either the PCI bus or the Local bus. When the I2O messaging unit functionality of the CY7C09449PV is to be used, the four FIFOs become part of the I2O messaging unit of the CY7C09449PV. The I2O messaging unit consists of the four FIFOs and the I2O system interrupt registers. The shared memory of the CY7C09449PV may be used to store I2O message frame buffers while most of shared memory is still available for generals purpose use. Efficient I2O messaging is realized when the local processor uses the CY7C09449PV direct access mechanism. It can be used to retrieve and post I2O message pointers to other I2O agents. Data transfer of the messages themselves is made very efficient using the CY7C09449PV PCI DMA controller to burst the message frames to other I2O agents.

Interprocess communication is supported by two resources of the CY7C09449PV the mailbox registers and the arbitration flags. By writing to the mailbox registers, a method is available for the local processor to pass data while causing an interrupt to the host, and vice versa. This is enabled by the interrupt mask located in the CY7C09449PV Operations Registers. The arbitration flags are four pairs of bits that can be used to manage resource allocation and sharing between software and system processes.

The CY7C09449PV includes an interrupt controller. There are separate interrupt mask and command/status registers for the

PCI bus and the Local bus. The interrupt sources are DMA completion, mailbox, FIFO not empty also for I2O , FIFO overflow, PCI master abort, PCI target abort, and there is an external interrupt input pin. This interrupt controller is used to signal interrupts onto the PCI bus and the Local bus. The CY7C09449PV interrupt controller does not perform the interrupt controller function for the PCI bus system. Standard PC PCI systems include this function embedded systems may need to implement this function.

An I2C-compatible serial interface is provided to allow the use of a serial EEPROM for non-volatile storage of CY7C09449PV initialization parameters. The parameters are PCI configuration and local bus settings. The CY7C09449PV will optionally access the EEPROM after reset and download initialization information before responding to PCI or local bus transactions. A wide variety of available I2C-compatible serial components are available to the local and host processor when connected through this interface.

The CY7C09449PV local bus is a flexible, configurable interface that is designed to readily connect to many industry standard microprocessors. In most cases, no external interface logic “glue” is needed.

The following block diagram illustrates a generic application for the CY7C09449PV.

Page 2 of 50

PCI System Bus

Processor Local Bus

CY7C09449PV-AC

PCI Add-In Card or PCI System Host

CY7C09449PV
128K Bit Shared Memory

Processor Power QUICC, 80x86, DSP, etc.

Memory SRAM, DRAM, FLASH, etc.

Peripherals Mass Storage,

ATM, Special, etc.
3042APP.VSD DB 6/02

Page 3 of 50

Pin Configuration

ADR[9]

VSS12

VDD1

ADR[8]

ADR[7]

ADR[6]
14 BURST_STYLE Defines the data ordering protocol of bursts on the local bus. 0 = normal linear bursts default 1 = 486 style burst byte ordering in a burst is 048C 40C8 8C04 C840
13 INT_POL Defines the polarity of the IRQ_OUT output signal. 0 = Active LOW interrupt to the local processor default 1 = Active HIGH interrupt to the local processor
12 BLAST_POL Defines the polarity of the BLAST input signal. 0 = Active LOW default 1 = Active HIGH
11 ALE_POL Defines the polarity of the ALE input signal. 0 = Active LOW1 = Active HIGH default
10 RDYOUT_POL Defines the polarity of the RDY_OUT output signal. 0 = Active LOW default 1 = Active HIGH
9:8 BW Defines the data bus width of the local processor interface. 00 = 8 bit10 = 32 bit 01 = 16 bit11 = 32 bit with encoded byte enables per Motorola protocol default
7 BLASTMODE Determines the function of the BLAST input signal. 0 = BLAST is active only during the last transaction of the burst default 1 = BLAST is active throughout the entire burst, and goes inactive when with RDY_IN or RDY_IN become inactive on the last read or write of the burst. -- DO NOT set BLASTMODE = 1 when XTND_RDY_OUT =
6 BEMODE Determines the byte enable encoding for 16 and 32 bit Motorola modes. 0 = normal byte enables1 = Motorola byte enable encoding. default

Page 39 of 50

CY7C09449PV-AC
5:4 RWMODE Defines how the READ, WRITE, and address STROBE input signals are interpreted internally and defines the Internal Address Strobe. The active polarity of STROBE is determined by ASMODE. ‘01’ is default.

Pin Name

RWMODE = 00

RWMODE = 01

RWMODE = 1X

READ

Not Used

READ data used as Internal Strobe

WRITE

Not Used

WRITE data used as Internal Strobe

STROBE

Internal Address Strobe

Internal Address Strobe Not used as Internal Address Strobe
3:2 ASMODE Bit 2 defines the polarity of STROBE input signal. And bit 3 defines the edge of CLKIN used to sample the Internal Address Strobe see field RWMODE for a defining characteristic of the Internal Address Strobe x0 = STROBE is active LOW default x1 = STROBE is active HIGH 0x = Internal Address Strobe rising edge sampled default 1x = Internal Address Strobe falling edge sampled
1 DDIN Delayed Data Input -- Defines protocol for validated input data. 0 = input data is valid during the current cycle when RDY_IN, RDY_IN, and RDY_OUT are active. default 1 = input data is valid one cycle after when RDY_IN, RDY_IN, and RDY_OUT are active.
0 DDOUT Delayed Data Output -- Defines protocol for validated output data. 0 = output data is valid during current cycle when RDY_IN, RDY_IN, and RDY_OUT are active. default 1 = output data is valid one cycle after when RDY_IN, RDY_IN, and RDY_OUT are active.

Page 40 of 50

CY7C09449PV-AC

Performance Characteristics

Absolute Maximum Ratings [4]

Storage Temperature to +125°C

Ambient Temperature Under Bias................. to +85°C Max Operating Current IDD [5,6] mA Voltage on Any VDD Pin Referenced to VSS to +4.0V Voltage on Any Signal Pin Referenced to +7.0V

Recommended Operating Environment

Ambient Operating Temperature................... TA0°C to +70°C

Supply Voltage to +3.6V

Ground Voltage Reference

FCLK PCI Clock Input Frequency ...... CLK0 MHz to 33 MHz

FCLKIN Local Bus

Clock

Input
Ordering Information
Ordering Code CY7C09449PV-AC

Package Name

Package Type

TQFP160 160-Pin Plastic Thin Quad Flat Pack

Operating Range
0°C to +70°C

Package Diagram

Pin 1

Pin 160

Page 48 of 50

Package Diagram continued

CY7C09449PV-AC

Page 49 of 50

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C09449PV-AC

Document Title CY7C09449PV-AC 128Kb Dual-Port SRAM with PCI Bus Controller PCI-DP Document Number 38-06061

ECN NO.

Issue Date

Orig. of Change

Description of Change
113168 02/14/02

DSG Change from Spec number 38-01014 to 38-05172

Change from Spec number 38-05172 to 38-06061
122309 12/27/02

RBI Power up requirements added to Absolute Maximum Ratings Information

Page 50 of 50

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C09449PV-AC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C09449PV-AC 507873