CY7C056V-12AXC

CY7C056V-12AXC Datasheet

CY7C056V CY7C057V CY7C037V CY7C038V3.3V 16K/32K x 36 FLEx36 Asynchronous Dual-Port Static RAM

Part	Datasheet
CY7C056V-12AXC	CY7C056V-12AXC (pdf)

PDF Datasheet Preview
CY7C056V CY7C057V CY7C037V CY7C038V3.3V 16K/32K x 36 FLEx36 Asynchronous Dual-Port Static RAM CY7C056V CY7C057V 3.3V 16K/32K x 36 FLEx36 Asynchronous Dual-Port Static • True dual-ported memory cells that allow simultaneous access of the same memory location • 16K x 36 organization CY7C056V • 32K x 36 organization CY7C057V • 0.25-micron CMOS for optimum speed/power • High-speed access 12/15/20 ns • Low operating power Active ICC = 250 mA typical Standby ISB3 = 10 µA typical • Fully asynchronous operation • Automatic power-down • Expandable data bus to 72 bits or more using Master/Slave Chip Select when using more than one device Logic Block Diagram • On-Chip arbitration logic • Semaphores included to permit software handshaking between ports • INT flag for port-to-port communication • Byte Select on Left Port • Bus Matching on Right Port • Depth Expansion via dual chip enables • Pin select for Master or Slave • Commercial and Industrial Temperature Ranges • Available in 144-Pin TQFP or 172-Ball BGA • Pb-Free packages available • Compact packages: 144-Pin TQFP 20 x 20 x mm 172-Ball BGA 1.0-mm pitch 15 x 15 x.51 mm R/WL CE0L CE1L OEL Left Port Control Logic I/O Control I/O Control Right Port Control Logic Match R/WR CE0R CE1R OER BA WA 9/18/36 I/OR BM SIZE 14/15 Address Decode True Dual-Ported RAM Array Address Decode 14/15 14/15 14/15 SEML BUSYL[2] INTL Notes for 16K for 32K devices. BUSY is an output in Master mode and an input in Slave mode. Interrupt Semaphore Arbitration SEMR BUSYR[2] INTR Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Functional Description The CY7C056V and CY7C057V are low-power CMOS 16K and 32K x 36 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 36-bit dual-port static RAMs or multiple devices can be combined in order to function as a 72-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 72-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Note CE is LOW when CE0 VIL and CE1 VIH. CY7C056V Ordering Information Speed ns 12 Ordering Code CY7C056V-12AC CY7C056V-12AXC CY7C056V-12BBC CY7C056V-15AC CY7C056V-15AXC CY7C056V-15BBC CY7C056V-20AC CY7C056V-20BBC Speed ns 12 15 Ordering Code CY7C057V-12AC CY7C057V-12AXC CY7C057V-12BBC CY7C057V-15AC CY7C057V-15AXC CY7C057V-15AI CY7C057V-15AXI CY7C057V-15BBC CY7C057V-15BBI CY7C057V-20AC CY7C057V-20BBC CY7C056V CY7C057V Package Name A144 BB172 A144 BB172 A144 BB172 Package Type 144-Pin Thin Quad Flat Pack 144-Pin Pb-Free Thin Quad Flat Pack 172-Ball Grid Array BGA 144-Pin Thin Quad Flat Pack 144-Pin Pb-Free Thin Quad Flat Pack 172-Ball Grid Array BGA 144-Pin Thin Quad Flat Pack 172-Ball Grid Array BGA Package Name A144 BB172 A144 BB172 A144 BB172 Package Type 144-Pin Thin Quad Flat Pack 144-Pin Pb-Free Thin Quad Flat Pack 172-Ball Grid Array BGA 144-Pin Thin Quad Flat Pack 144-Pin Pb-Free Thin Quad Flat Pack 144-Pin Thin Quad Flat Pack 144-Pin Pb-Free Thin Quad Flat Pack 172-Ball Grid Array BGA 172-Ball Grid Array BGA 144-Pin Thin Quad Flat Pack 172-Ball Grid Array BGA Operating Range Commercial Commercial Commercial Operating Range Commercial Commercial Industrial Commercial Industrial Commercial Page 20 of 23 [+] Feedback Package Diagrams 144-Pin Plastic Thin Quad Flat Pack TQFP A144 144-Pin Pb-Free Plastic Thin Quad Flat Pack TQFP A144 CY7C056V CY7C057V 51-85047-A Page 21 of 23 [+] Feedback Package Diagrams continued 172-Ball FBGA 15 x 15 x mm BB172 CY7C056V CY7C057V 51-85114-B FLEx36 is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 22 of 23 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C056V CY7C057V Document History Page Document Title CY7C056V/CY7C057V 3.3V 16K/32K x 36 FLEx36 Asynchronous Dual-Port Static RAM Document Number 38-06055 Issue Date Orig. of Change Description of Change 110214 12/16/01 SZV Change from Spec number 38-00742 to 38-06055 122305 12/27/02 RBI Power up requirements added to Maximum Ratings Information 393770 See ECN Added Pb-Free parts to ordering information: CY7C056V-12AXC, CY7C056V-15AXC, CY7C057V-12AXC, CY7C057V-15AXC, CY7CO57V-15AXI Page 23 of 23 [+] Feedback

PDF Datasheet Preview

CY7C056V CY7C057V CY7C037V CY7C038V3.3V 16K/32K x 36 FLEx36 Asynchronous Dual-Port Static RAM

CY7C056V CY7C057V
3.3V 16K/32K x 36 FLEx36 Asynchronous Dual-Port Static
• True dual-ported memory cells that allow simultaneous access of the same memory location
• 16K x 36 organization CY7C056V
• 32K x 36 organization CY7C057V
• 0.25-micron CMOS for optimum speed/power
• High-speed access 12/15/20 ns
• Low operating power

Active ICC = 250 mA typical Standby ISB3 = 10 µA typical
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 72 bits or more using Master/Slave Chip Select when using more than one device

Logic Block Diagram
• On-Chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Byte Select on Left Port
• Bus Matching on Right Port
• Depth Expansion via dual chip enables
• Pin select for Master or Slave
• Commercial and Industrial Temperature Ranges
• Available in 144-Pin TQFP or 172-Ball BGA
• Pb-Free packages available
• Compact packages:
144-Pin TQFP 20 x 20 x mm 172-Ball BGA 1.0-mm pitch 15 x 15 x.51 mm

R/WL CE0L CE1L OEL

Left

Port

Control Logic

I/O Control

I/O Control

Right Port Control Logic

Match

R/WR

CE0R CE1R OER BA WA
9/18/36

I/OR

BM SIZE
14/15

Address Decode

True Dual-Ported RAM Array

Address Decode
14/15
14/15
14/15

SEML BUSYL[2] INTL

Notes for 16K for 32K devices. BUSY is an output in Master mode and an input in Slave mode.

Interrupt Semaphore Arbitration

SEMR BUSYR[2]

INTR

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Functional Description

The CY7C056V and CY7C057V are low-power CMOS 16K and 32K x 36 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 36-bit dual-port static RAMs or multiple devices can be combined in order to function as a 72-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 72-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory.

Note CE is LOW when CE0 VIL and CE1 VIH.

CY7C056V
Ordering Information

Speed ns 12
Ordering Code CY7C056V-12AC CY7C056V-12AXC CY7C056V-12BBC CY7C056V-15AC CY7C056V-15AXC CY7C056V-15BBC CY7C056V-20AC CY7C056V-20BBC

Speed ns 12 15
Ordering Code CY7C057V-12AC CY7C057V-12AXC CY7C057V-12BBC CY7C057V-15AC CY7C057V-15AXC CY7C057V-15AI CY7C057V-15AXI CY7C057V-15BBC CY7C057V-15BBI CY7C057V-20AC CY7C057V-20BBC

CY7C056V CY7C057V

Package Name A144 BB172 A144 BB172 A144 BB172

Package Type 144-Pin Thin Quad Flat Pack 144-Pin Pb-Free Thin Quad Flat Pack 172-Ball Grid Array BGA 144-Pin Thin Quad Flat Pack 144-Pin Pb-Free Thin Quad Flat Pack 172-Ball Grid Array BGA 144-Pin Thin Quad Flat Pack 172-Ball Grid Array BGA

Package Name A144 BB172 A144 BB172 A144 BB172

Package Type 144-Pin Thin Quad Flat Pack 144-Pin Pb-Free Thin Quad Flat Pack 172-Ball Grid Array BGA 144-Pin Thin Quad Flat Pack 144-Pin Pb-Free Thin Quad Flat Pack 144-Pin Thin Quad Flat Pack 144-Pin Pb-Free Thin Quad Flat Pack 172-Ball Grid Array BGA 172-Ball Grid Array BGA 144-Pin Thin Quad Flat Pack 172-Ball Grid Array BGA

Operating Range

Commercial

Commercial

Commercial

Operating Range

Commercial

Commercial Industrial Commercial Industrial Commercial

Page 20 of 23 [+] Feedback

Package Diagrams
144-Pin Plastic Thin Quad Flat Pack TQFP A144 144-Pin Pb-Free Plastic Thin Quad Flat Pack TQFP A144

CY7C056V CY7C057V
51-85047-*A

Page 21 of 23 [+] Feedback

Package Diagrams continued
172-Ball FBGA 15 x 15 x mm BB172

CY7C056V CY7C057V
51-85114-*B

FLEx36 is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.

Page 22 of 23

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback

CY7C056V CY7C057V

Document History Page

Document Title CY7C056V/CY7C057V 3.3V 16K/32K x 36 FLEx36 Asynchronous Dual-Port Static RAM Document Number 38-06055

Issue Date

Orig. of Change Description of Change
110214 12/16/01

SZV Change from Spec number 38-00742 to 38-06055
122305 12/27/02

RBI Power up requirements added to Maximum Ratings Information
393770 See ECN
Added Pb-Free parts to ordering information:

CY7C056V-12AXC, CY7C056V-15AXC, CY7C057V-12AXC,

CY7C057V-15AXC, CY7CO57V-15AXI

Page 23 of 23 [+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C056V-12AXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C056V-12AXC 507862