CTSLV392NG

CTSLV392NG Datasheet

CTSLV392

Part	Datasheet
CTSLV392NG	CTSLV392NG (pdf)

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CTSLV392 LVPECL Divide by 1, Divide by 2 Clock Generator w/ Selectable Enable MLP8 BLOCK DIAGRAM  Selectable Divide Ratio  Selectable Enable Priority and Threshold CMOS or PECL  3.0V to 5.5V Power Supply  -145dBc/Hz ÷1 Typical Noise Floor  -151dBc/Hz ÷2 Typical Noise Floor  High BW [1.5GHz ÷1 , 3.0GHz ÷2 ]  ROHS compliant Pb Free Packages The CTSLV392 is a ÷1 or ÷2 clock generation part specifically designed to accommodate Colpitts or Pierce based oscillators. Features are incorporated to reduce board components. A voltage reference and input biasing allows for easy oscillator interface. The CTSLV392 provides a ÷ 2 mode of operation for more frequency options and is selectable with a single connection. A selectable enable is also provided which doubles as a reset when the CTSLV392 is in ÷2 mode. With a single connection, the enable can be selected to operate as active high or active low. ENGINEERING NOTES The CTSLV392 is a specialized ÷1 or ÷2 clock generation part including an enable/reset function. The divide ratio is selected with the DIV-SEL pin/pad. When DIV-SEL is open NC , the CTSLV392 functions as a standard receiver. If DIV-SEL is connected to VEE, it functions as a ÷2 divider. A selectable enable is provided which also functions as a reset when the ÷2 mode is selected. Enable EN functionality is selected with the EN-SEL pin/pad which has three valid states open NC , VEE, or connected to VEE via a resistor. Leaving EN-SEL open or connecting it to VEE will select the EN pin/pad to function as an active high CMOS/TTL enable. When EN-SEL is open, an internal pull-up resistor is selected which enables the outputs whenever EN is left open. When EN-SEL is connected to VEE, an internal pull-down resistor is selected which disables the outputs whenever EN is left open. Connecting the EN-SEL to VEE with a resistor will select the EN pin/pad to function as an active low PECL/ECL enable with an internal pull-down resistor. In this mode, outputs are enabled when EN is left open NC . This default logic condition can be overridden by connecting the EN to VCC with an external resistor of Refer to the enable truth table on the next page for detailed operation. The CTSLV392 provides a VBB with an internal bias resistor from D to VBB. This feature allows AC coupling with minimal external components. The VBB pin supports 1.5mA sink/source current and should be bypassed to ground or VCC with a uF capacitor. North Americas +1-800-757-6686 • International +1-508-435-6831 • Asia +65-655-17551 • Specifications are subject to change without notice. 1 CTSLV392 LVPECL Divide by 1, Divide by 2 Clock Generator w/ Selectable Enable MLP8 Divide Truth Table DIV-SEL ÷Ratio VEE1 1 DIV-SEL connection must be EN-SEL NC VEE to VEE Enable Truth Table EN CMOS Low or VEE CMOS High, VCC or NC CMOS Low, VEE or NC CMOS High or VCC PECL Low, VEE or NC PECL High or VCC Q Low Data Low Data Low Data Low Data Low Data Low Data Figure 1 illustrates the timing sequences for the CTSLV392 in the ÷1 mode which is determined by leaving the DIV-SEL open NC . It also illustrates the enable in the active High mode being controlled by a CMOS signal. This mode is determined by leaving the EN-SEL open NC . Figure 1 Figure 2 illustrates the timing sequences for the CTSLV392 in the ÷2 mode which is determined by connecting the DIV-SEL to VEE. It also illustrates the enable in the active Low mode being controlled by a PECL signal. This mode is determined by connecting the EN-SEL to VEE via resistor. Figure 2 PART ORDERING INFORMATION CTSLV392NG Package MLP8 Marking P1G / YWW North Americas +1-800-757-6686 • International +1-508-435-6831 • Asia +65-655-17551 • Specifications are subject to change without notice. 6

PDF Datasheet Preview

CTSLV392

LVPECL Divide by 1, Divide by 2 Clock Generator w/ Selectable Enable

MLP8

BLOCK DIAGRAM
 Selectable Divide Ratio
 Selectable Enable Priority and Threshold

CMOS or PECL
 3.0V to 5.5V Power Supply
 -145dBc/Hz ÷1 Typical Noise Floor
 -151dBc/Hz ÷2 Typical Noise Floor
 High BW [1.5GHz ÷1 , 3.0GHz ÷2 ]
 ROHS compliant Pb Free Packages

The CTSLV392 is a ÷1 or ÷2 clock generation part specifically designed to accommodate Colpitts or Pierce based oscillators. Features are incorporated to reduce board components. A voltage reference and input biasing allows for easy oscillator interface.

The CTSLV392 provides a ÷ 2 mode of operation for more frequency options and is selectable with a single connection. A selectable enable is also provided which doubles as a reset when the CTSLV392 is in ÷2 mode. With a single connection, the enable can be selected to operate as active high or active low.

ENGINEERING NOTES

The CTSLV392 is a specialized ÷1 or ÷2 clock generation part including an enable/reset function. The divide ratio is selected with the DIV-SEL pin/pad. When DIV-SEL is open NC , the CTSLV392 functions as a standard receiver. If DIV-SEL is connected to VEE, it functions as a ÷2 divider.

A selectable enable is provided which also functions as a reset when the ÷2 mode is selected. Enable EN functionality is selected with the EN-SEL pin/pad which has three valid states open NC , VEE, or connected to VEE via a resistor. Leaving EN-SEL open or connecting it to VEE will select the EN pin/pad to function as an active high CMOS/TTL enable. When EN-SEL is open, an internal pull-up resistor is selected which enables the outputs whenever EN is left open. When EN-SEL is connected to VEE, an internal pull-down resistor is selected which disables the outputs whenever EN is left open.

Connecting the EN-SEL to VEE with a resistor will select the EN pin/pad to function as an active low PECL/ECL enable with an internal pull-down resistor. In this mode, outputs are enabled when EN is left open NC . This default logic condition can be overridden by connecting the EN to VCC with an external resistor of Refer to the enable truth table on the next page for detailed operation.

The CTSLV392 provides a VBB with an internal bias resistor from D to VBB. This feature allows AC coupling with minimal external components. The VBB pin supports 1.5mA sink/source current and should be bypassed to ground or VCC with a uF capacitor.

North Americas +1-800-757-6686
• International +1-508-435-6831
• Asia +65-655-17551
•

Specifications are subject to change without notice. 1

CTSLV392

LVPECL Divide by 1, Divide by 2 Clock Generator w/ Selectable Enable

MLP8

Divide Truth Table

DIV-SEL
÷Ratio

VEE1
1 DIV-SEL connection must be

EN-SEL NC VEE
to VEE

Enable Truth Table EN

CMOS Low or VEE CMOS High, VCC or NC CMOS Low, VEE or NC

CMOS High or VCC PECL Low, VEE or NC

PECL High or VCC

Q Low Data Low Data Low Data

Low Data Low Data Low Data

Figure 1 illustrates the timing sequences for the CTSLV392 in the ÷1 mode which is determined by leaving the DIV-SEL open NC . It also illustrates the enable in the active High mode being controlled by a CMOS signal. This mode is determined by leaving the EN-SEL open NC .

Figure 1

Figure 2 illustrates the timing sequences for the CTSLV392 in the ÷2 mode which is determined by connecting the DIV-SEL to VEE. It also illustrates the enable in the active Low mode being controlled by a PECL signal. This mode is determined by connecting the EN-SEL to VEE via resistor.

Figure 2
PART ORDERING INFORMATION

CTSLV392NG

Package MLP8

Marking P1G / YWW

North Americas +1-800-757-6686
• International +1-508-435-6831
• Asia +65-655-17551
•

Specifications are subject to change without notice. 6

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CTSLV392NG Datasheet file may be downloaded here without warranties.

Datasheet ID: CTSLV392NG 507355