CY7B991-2JC

CY7B991-2JC Datasheet

CY7B991 CY7B992

Part	Datasheet
CY7B991-2JC	CY7B991-2JC (pdf)

Related Parts	Information
CY7B991-7JC	CY7B991-7JC

PDF Datasheet Preview
CY7B991 CY7B992 Programmable Skew Clock Buffer • All output pair skew <100 ps typical 250 max. • to 80-MHz output operation • User-selectable output functions Selectable skew to 18 ns Inverted and non-inverted Operation at and input frequency Operation at 2x and 4x input frequency input as low as MHz • Zero input to output delay • 50% duty-cycle outputs • Outputs drive terminated lines • Low operating current • 32-pin PLCC/LCC package • Jitter < 200 ps peak-to-peak < 25 ps RMS • Compatible with a Pentium -based processor Functional Description The CY7B991 and CY7B992 Programmable Skew Clock Buffers PSCB offer user-selectable control over system clock functions. These multiple-output clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance computer systems. Eight individual drivers, arranged as four pairs of user-controllable outputs, can each drive terminated transmission lines with impedances as low as while delivering minimal and specified output skews and full-swing logic levels CY7B991 TTL or CY7B992 CMOS . Each output can be hardwired to one of nine delay or function configurations. Delay increments of to ns are determined by the operating frequency with outputs able to skew up to ±6 time units from their nominal “zero” skew position. The completely integrated PLL allows external load and transmission line delay effects to be canceled. When this “zero delay” capability of the PSCB is combined with the selectable output skew functions, the user can create output-to-output delays of up to ±12 time units. Divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions allow distribution of a low-frequency clock that can be multiplied by two or four at the clock destination. This facility minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility. Logic Block Diagram Pin Configuration TEST FB REF PHASE FREQ FILTER DET VCO AND TIME UNIT GENERATOR 4F0 4F1 SELECT INPUTS THREE LEVEL 3F0 3F1 2F0 2F1 SKEW SELECT MATRIX PLCC/LCC 3F0 FS VCCQ REF GND TEST 2F1 4 3 2 1 32 31 30 3F1 5 29 2F0 4F0 6 28 GND 4F1 7 27 1F1 VCCQ 8 26 1F0 CY7B991 VCCN 9 CY7B992 25 VCCN 4Q1 10 3Q1 4Q0 11 24 1Q0 23 1Q1 GND 12 22 GND Ordering Information Accuracy ps 250 500 250 500 Ordering Code Package Name J65 L55 J65 L55 Package Type Operating Range 32-Lead Plastic Leaded Chip Carrier Commercial 32-Lead Plastic Leaded Chip Carrier Commercial 32-Lead Plastic Leaded Chip Carrier Industrial 32-Lead Plastic Leaded Chip Carrier Commercial 32-Lead Plastic Leaded Chip Carrier Industrial 32-Pin Rectangular Leadless Chip Carrier Military 32-Lead Plastic Leaded Chip Carrier Commercial 32-Lead Plastic Leaded Chip Carrier Commercial 32-Lead Plastic Leaded Chip Carrier Industrial 32-Lead Plastic Leaded Chip Carrier Commercial 32-Lead Plastic Leaded Chip Carrier Industrial 32-Pin Rectangular Leadless Chip Carrier Military MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter VOH VOL VIH VIL VIHH VIMM VILL IIH IIL IIHH IIMM IILL ICCQ ICCN Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Page 13 of 15 Package Diagrams 32-Lead Plastic Leaded Chip Carrier CY7B991 CY7B992 32-Pin Rectangular Leadless Chip Carrier MIL-STD-1835 C-12 Page 14 of 15 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7B991 CY7B992 Document Title CY7B991/CY7B992 Programmable Skew Clock Buffer PSCB Document Number 38-07138

PDF Datasheet Preview

CY7B991 CY7B992

Programmable Skew Clock Buffer
• All output pair skew <100 ps typical 250 max.
• to 80-MHz output operation
• User-selectable output functions

Selectable skew to 18 ns Inverted and non-inverted Operation at and input frequency Operation at 2x and 4x input frequency input as low
as MHz
• Zero input to output delay
• 50% duty-cycle outputs
• Outputs drive terminated lines
• Low operating current
• 32-pin PLCC/LCC package
• Jitter < 200 ps peak-to-peak < 25 ps RMS
• Compatible with a Pentium -based processor

Functional Description

The CY7B991 and CY7B992 Programmable Skew Clock Buffers PSCB offer user-selectable control over system clock
functions. These multiple-output clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance computer systems. Eight individual drivers, arranged as four pairs of user-controllable outputs, can each drive terminated transmission lines with impedances as low as while delivering minimal and specified output skews and full-swing logic levels CY7B991 TTL or CY7B992 CMOS .

Each output can be hardwired to one of nine delay or function configurations. Delay increments of to ns are determined by the operating frequency with outputs able to skew up to ±6 time units from their nominal “zero” skew position. The completely integrated PLL allows external load and transmission line delay effects to be canceled. When this “zero delay” capability of the PSCB is combined with the selectable output skew functions, the user can create output-to-output delays of up to ±12 time units.

Divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions allow distribution of a low-frequency clock that can be multiplied by two or four at the clock destination. This facility minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility.

Logic Block Diagram

Pin Configuration

TEST

FB REF

PHASE

FREQ FILTER DET

VCO AND TIME UNIT GENERATOR
4F0 4F1

SELECT INPUTS THREE LEVEL 3F0 3F1
2F0 2F1

SKEW SELECT MATRIX

PLCC/LCC
3F0 FS VCCQ REF GND TEST 2F1
4 3 2 1 32 31 30
3F1 5
29 2F0
4F0 6
28 GND
4F1 7
27 1F1

VCCQ 8
26 1F0

CY7B991

VCCN 9

CY7B992
25 VCCN
4Q1 10 3Q1
4Q0 11
24 1Q0 23 1Q1

GND 12
22 GND
Ordering Information

Accuracy ps 250 500
250 500
Ordering Code

Package Name J65 L55 J65 L55

Package Type

Operating Range
32-Lead Plastic Leaded Chip Carrier

Commercial
32-Lead Plastic Leaded Chip Carrier

Commercial
32-Lead Plastic Leaded Chip Carrier

Industrial
32-Lead Plastic Leaded Chip Carrier

Commercial
32-Lead Plastic Leaded Chip Carrier

Industrial
32-Pin Rectangular Leadless Chip Carrier Military
32-Lead Plastic Leaded Chip Carrier

Commercial
32-Lead Plastic Leaded Chip Carrier

Commercial
32-Lead Plastic Leaded Chip Carrier

Industrial
32-Lead Plastic Leaded Chip Carrier

Commercial
32-Lead Plastic Leaded Chip Carrier

Industrial
32-Pin Rectangular Leadless Chip Carrier Military

MILITARY SPECIFICATIONS Group A Subgroup Testing

DC Characteristics

Parameter

VOH VOL VIH VIL VIHH VIMM VILL IIH IIL IIHH IIMM IILL ICCQ ICCN

Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3

Page 13 of 15

Package Diagrams
32-Lead Plastic Leaded Chip Carrier

CY7B991 CY7B992
32-Pin Rectangular Leadless Chip Carrier

MIL-STD-1835 C-12

Page 14 of 15

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7B991 CY7B992

Document Title CY7B991/CY7B992 Programmable Skew Clock Buffer PSCB Document Number 38-07138

More datasheets: ANX-1390-G | ANX-1390-B | ANX-1390 | FDS7288N3 | M33591 SL001 | M33591 SL002 | M33591 SL005 | TEL0121 | S560-6100-A1-F | CY7B991-7JC

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7B991-2JC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7B991-2JC 507839