CY62148DV30
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CY62148DV30LL-70ZSXAT (pdf) |
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CY62148DV30LL-70ZSXA |
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CY62148DV30 4-Mbit 512K x 8 Static RAM • Temperature Ranges Industrial to 85°C Automotive-A to 85°C • Very high speed 55 ns Wide voltage range 2.20V 3.60V • Pin-compatible with CY62148CV25, CY62148CV30 and CY62148CV33 • Ultra low active power Typical active current mA f = 1 MHz Typical active current 8 mA f = fmax 55-ns speed • Ultra low standby power • Easy memory expansion with CE, and OE features • Automatic power-down when deselected • CMOS for optimum speed/power • Available in Pb-free and non Pb-free 36-ball VFBGA, Pb-free 32-pin TSOPII and 32-pin SOIC packages Logic Block Diagram Functional Description[1] The CY62148DV30 is a high-performance CMOS static RAM organized as 512K words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption. The device can be put into standby mode reducing power consumption when deselected CE HIGH .The eight input and output pins IO0 through IO7 are placed in a high-impedance state when: • Deselected CE HIGH • Outputs are disabled OE HIGH • When the write operation is active CE LOW and WE LOW Write to the device by taking Chip Enable CE and Write Enable WE inputs LOW. Data on the eight IO pins IO0 through IO7 is then written into the location specified on the address pins A0 through A18 . Read from the device by taking Chip Enable CE and Output Enable OE LOW while forcing Write Enable WE HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the IO pins. AA10 AA78 A9 A10 AA1121 CE WE OE ROW DECODER SENSE AMPS Data in Drivers 512K x 8 ARRAY COLUMN DECODER POWER DOWN IO 0 IO 1 IO 2 IO 3 IO 4 IO 5 IO 6 IO 7 A13 A14 A15 A16 A17 A18 Note For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Pin Configuration[2, 3] 36-ball VFBGA Pinout Top View A0 A1 NC A3 A6 A8 IO 4 A2 WE A4 A7 IO 0 DNU A5 A18 A17 IO 7 OE CE A16 A15 IO 3 A10 A11 A12 A13 A14 CY62148DV30 32-pin SOIC / TSOP II Pinout Top View A17 1 A16 2 A14 3 A12 4 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 IO 0 13 IO 1 14 IO 2 15 VSS 16 Ordering Information Speed ns Ordering Code Package Diagram Package Type 55 CY62148DV30LL-55BVI 51-85149 36-ball VFBGA 6 x 8 x 1 mm CY62148DV30LL-55BVXI 36-ball VFBGA 6 x 8 x 1 mm Pb-free CY62148DV30L-55ZSXI 51-85095 32-pin TSOP II Pb-free CY62148DV30LL-55ZSXI CY62148DV30LL-55SXI 51-85081 32-pin SOIC Pb-free 70 CY62148DV30LL-70ZSXI 51-85095 32-pin TSOP II Pb-free CY62148DV30LL-70ZSXA 51-85095 32-pin TSOP II Pb-free Contact your local Cypress sales representative for availability of these parts Package Diagrams Figure 36-ball VFBGA 6 x 8 x 1 mm , 51-85149 TOP VIEW A1 CORNER 12 3 4 5 6 A B C D E F G H Operating Range Industrial Industrial Automotive-A BOTTOM VIEW A1 CORNER M C M C A B Ø0.30±0.05 36X 6 54 3 2 1 A B C D E F G H B 0.15 4X C MAX. SEATING PLANE C 51-85149-*C MAX. Page 8 of 10 Package Diagrams continued Figure 32-pin TSOP II, 51-85095 CY62148DV30 Figure 32-pin 450 MIL Molded SOIC, 51-85081 51-85095-** BSC. MIN. MAX. SEATING PLANE 51-85081-*B MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Added Pb-free ordering information Removed 32-pin STSOP package 498575 See ECN NXR Added Automotive-A Operating Range Removed SOIC package from Product Offering Updated Ordering Information Table 729917 See ECN VKN Added SOIC package and its related information Updated Ordering Information Table Page 10 of 10 |
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