CY7C187-15PXC

CY7C187-15PXC Datasheet

CY7C187

Part	Datasheet
CY7C187-15PXC	CY7C187-15PXC (pdf)

PDF Datasheet Preview
CY7C187 64K x 1 Static RAM • High speed 15 ns • CMOS for optimum speed/power • Low active power 495 mW • Low standby power 110 mW • TTL compatible inputs and outputs • Automatic power-down when deselected • Available in Pb-free and non Pb-free 22-pin 300-Mil Molded DIP and 24-pin 300-Mil Molded SOJ Logic Block Diagram Functional Description The CY7C187 is a high-performance CMOS static RAM organized as 65,536 words x 1 bit. Easy memory expansion is provided by an active LOW Chip Enable CE and tri-state drivers. The CY7C187 has an automatic power-down feature, reducing the power consumption by 56% when deselected. Writing to the device is accomplished when the Chip Enable CE and Write Enable WE inputs are both LOW. Data on the input pin DIN is written into the memory location specified on the address pins A0 through A15 . Reading the device is accomplished by taking the Chip Enable CE LOW, while Write Enable WE remains HIGH. Under these conditions, the contents of the memory location specified on the address pin will appear on the data output DOUT pin. The output pin stays in high-impedance state when Chip Enable CE is HIGH or Write Enable WE is LOW. The CY7C187 utilizes a die coat to insure alpha immunity. Pin Configurations ROW DECODER A4 A5 A6 A7 A8 A9 A10 A11 SENSE AMPS INPUT BUFFER A14 A15 16K x 1 ARRAY COLUMN DECODER POWER DOWN Selection Guide Maximum Access Time ns Maximum Operating Current mA Maximum CMOS Standby Current mA DO CE WE SOJ Top View DIP Top View A1 2 A2 3 A3 4 A4 5 A5 6 NC 7 A6 8 A7 9 DOUT 10 WE 11 GND 12 24 VCC 23 A15 22 A14 21 A13 20 A12 19 NC 18 A11 17 A10 16 A9 DOUT 9 15 A8 Ordering Information Speed ns Ordering Code CY7C187-15PXC CY7C187-25PC CY7C187-25VC CY7C187-25VXC CY7C187-35VXC CY7C187 Package Diagram 51-85012 51-85012 51-85030 51-85030 Package Type 22-pin 300-Mil Molded DIP Pb-free 22-pin 300-Mil Molded DIP 24-pin 300-Mil Molded SOJ 24-pin 300-Mil Molded SOJ Pb-free 24-pin 300-Mil Molded SOJ Pb-free Operating Range Commercial Commercial Package Diagrams 22-pin 300-Mil PDIP 51-85012 DIMENSIONS IN INCHES MIN. MAX. SEATING PLANE 3° MIN. 51-85012-A Page 7 of 9 Package Diagrams Continued 24-pin 300-mil SOJ 51-85030 PIN 1 ID CY7C187 DIMENSIONS IN INCHES[MM] MIN. MAX. REFERENCE JEDEC MO-088 PACKAGE WEIGHT 0.75gms V24.3 VZ24.3 PART # STANDARD PKG. LEAD FREE PKG. SEATING PLANE TYP. MIN. 51-85030-B All products and company names mentioned in this document may be the trademarks of their respective holders. Page 8 of 9 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C187 Document History Page Document Title CY7C187 64K x 1 Static RAM Document Number 38-05044 Issue ECN NO. Date Orig. of Change Description of Change Updated the Ordering Information Table Page 9 of 9

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CY7C187
64K x 1 Static RAM
• High speed 15 ns
• CMOS for optimum speed/power
• Low active power
495 mW
• Low standby power
110 mW
• TTL compatible inputs and outputs
• Automatic power-down when deselected
• Available in Pb-free and non Pb-free 22-pin 300-Mil

Molded DIP and 24-pin 300-Mil Molded SOJ

Logic Block Diagram

Functional Description

The CY7C187 is a high-performance CMOS static RAM organized as 65,536 words x 1 bit. Easy memory expansion is provided by an active LOW Chip Enable CE and tri-state drivers. The CY7C187 has an automatic power-down feature, reducing the power consumption by 56% when deselected.

Writing to the device is accomplished when the Chip Enable CE and Write Enable WE inputs are both LOW. Data on the input pin DIN is written into the memory location specified on the address pins A0 through A15 . Reading the device is accomplished by taking the Chip Enable CE LOW, while Write Enable WE remains HIGH. Under these conditions, the contents of the memory location specified on the address pin will appear on the data output DOUT pin. The output pin stays in high-impedance state when Chip Enable CE is HIGH or Write Enable WE is LOW.

The CY7C187 utilizes a die coat to insure alpha immunity.

Pin Configurations

ROW DECODER A4 A5 A6 A7 A8 A9 A10 A11

SENSE AMPS

INPUT BUFFER

A14 A15
16K x 1

ARRAY

COLUMN DECODER

POWER DOWN

Selection Guide

Maximum Access Time ns Maximum Operating Current mA Maximum CMOS Standby Current mA

DO CE WE

SOJ Top View

DIP Top View

A1 2 A2 3 A3 4

A4 5 A5 6 NC 7 A6 8 A7 9 DOUT 10

WE 11

GND 12
24 VCC
23 A15
22 A14
21 A13
20 A12
19 NC
18 A11
17 A10
16 A9

DOUT 9
15 A8
Ordering Information

Speed ns
Ordering Code

CY7C187-15PXC

CY7C187-25PC

CY7C187-25VC

CY7C187-25VXC

CY7C187-35VXC

CY7C187

Package Diagram 51-85012 51-85012 51-85030
51-85030

Package Type
22-pin 300-Mil Molded DIP Pb-free 22-pin 300-Mil Molded DIP 24-pin 300-Mil Molded SOJ 24-pin 300-Mil Molded SOJ Pb-free 24-pin 300-Mil Molded SOJ Pb-free

Operating Range

Commercial

Commercial

Package Diagrams
22-pin 300-Mil PDIP 51-85012

DIMENSIONS IN INCHES MIN. MAX.

SEATING PLANE
3° MIN.
51-85012-*A

Page 7 of 9

Package Diagrams Continued
24-pin 300-mil SOJ 51-85030 PIN 1 ID

CY7C187

DIMENSIONS IN INCHES[MM]

MIN. MAX.

REFERENCE JEDEC MO-088 PACKAGE WEIGHT 0.75gms

V24.3 VZ24.3

PART # STANDARD PKG. LEAD FREE PKG.

SEATING PLANE

TYP.

MIN.
51-85030-*B

All products and company names mentioned in this document may be the trademarks of their respective holders.

Page 8 of 9

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CY7C187

Document History Page

Document Title CY7C187 64K x 1 Static RAM Document Number 38-05044

Issue ECN NO. Date

Orig. of Change Description of Change
Updated the Ordering Information Table

Page 9 of 9

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C187-15PXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C187-15PXC 508076