CY29772AXIT

CY29772AXIT Datasheet


CY29772

Part Datasheet
CY29772AXIT CY29772AXIT CY29772AXIT (pdf)
Related Parts Information
CY29772AXI CY29772AXI CY29772AXI
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CY29772
• Output frequency range MHz to 200 MHz
• Input frequency range MHz to 125 MHz
• 2.5V or 3.3V operation
• Split 2.5V/3.3V outputs
• ±2% max. Output duty cycle variation
• 7 ps RMS typical Cycle-to-cycle jitter
• 6 ps RMS typical Period jitter
• 12 clock outputs drive up to 24 clock lines
• One feedback output
• Three reference clock inputs crystal or LVCMOS
• 300 ps max. output-output skew
• Phase-locked loop PLL bypass mode
• Spread Aware
• Output enable/disable
• Pin-compatible with MPC9772 and MPC972
• Industrial temperature range to +85°C
• 52-pin 1.0-mm TQFP package
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer

The CY29772 is a low-voltage high-performance 200-MHz PLL-based zero delay buffer designed for high-speed clock-distribution applications.

The CY29772 features one on-chip crystal oscillator and two LVCMOS reference clock inputs and provides 12 outputs partitioned in three banks of four outputs each. Each bank divides the VCO output per SEL A:C settings, see Functional Table. These dividers allow output to input ratios of 8:1, 6:1, 5:1, 4:1, 3:1, 8:3, 5:2, 2:1, 5:3, 3:2, 4:3, 5:4, 1:1, and Each LVCMOS-compatible output can drive series- or parallel-terminated transmission lines. For series-terminated transmission lines, each output can drive one or two traces, giving the device an effective fanout of

The PLL is ensured stable given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies from 8 MHz to 200 MHz. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by the feedback divider, see Frequency Table.

When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply.

Block Diagram

XIN XOUT VCO_SEL PLL_EN REF_SEL

TCLK0

TCLK1

TCLK_SEL

FB_IN

Phase Detector

FB_SEL2

MR#/OE

Power-On Reset

SELA 0,1

SELB 0,1

SELC 0,1

FB_SEL 0,1

SCLK SDATA
/4, /6, /8, /12 /4, /6, /8, /10
/2, /4, /6, /8
/4, /6, /8, /10

Sync Pulse Data Generator
0 /2 1

Output Disable 12 Circuitry

INV_CLK

Sync Frz

Sync Frz

Sync Frz

Sync Frz

Sync Frz

Sync Frz

Pin Configuration

SELB1 SELB0 SELA1 SELA0

QA3 VDDQA

QA2 VSS QA1 VDDQA QA0 VSS VCO_SEL

QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3

QC0 QC1 QC2 QC3 FB_OUT
Ordering Information

Part Number CY29772AI CY29772AIT Lead-free CY29772AXI CY29772AXIT

Package Type 52-pin TQFP 52-pin TQFP Tape and Reel
52-pin TQFP 52-pin TQFP Tape and Reel

Package Drawing and Dimension

Product Flow Industrial, to +85°C to 85°C

Industrial, to +85°C to 85°C
52-lead Thin Plastic Quad Flat Pack 10 x 10 x mm A52B
51-85158-**

Spread Aware is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.

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Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Document History Page

Document Title:CY29772 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Document Number 38-07572

Description of Change
129007 09/03/03

RGL New Data Sheet
395853 See ECN

Added Lead-free devices Added Jitter typical specs in the features section

CY29772

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Datasheet ID: CY29772AXIT 507740