CY29351AXI

CY29351AXI Datasheet

CY29351

Part	Datasheet
CY29351AXI	CY29351AXI (pdf)

Related Parts	Information
CY29351AXIT	CY29351AXIT

PDF Datasheet Preview
CY29351 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer • Output Frequency Range 25 MHz to 200 MHz • Input Frequency Range 25 MHz to 200 MHz • 2.5V or 3.3V Operation • Split 2.5V and 3.3V Outputs • Max Output Duty Cycle Variation • Nine Clock Outputs Drive up to 18 Clock Lines • Two Reference Clock Inputs LVPECL or LVCMOS • 150-ps Max Output-Output Skew • Phase-locked Loop PLL Bypass Mode • Spread Aware • Output Enable or Disable • Pin-compatible with MPC9351 • Industrial Temperature Range to +85°C • 32-pin 1.0-mm TQFP Package Logic Block Diagram Functional Description The CY29351 is a low voltage high performance 200 MHz PLL-based zero delay buffer designed for high speed clock distribution applications. The CY29351 features LVPECL and LVCMOS reference clock inputs and provides nine outputs partitioned in four banks of one, one, two, and five outputs. Bank A divides the VCO output by two or four while the other banks divide by four or eight per SEL A:D settings Table 3, “Function Table,” on page These dividers enable output to input ratios of 4:1, 2:1, 1:1, 1:2, and Each LVCMOS compatible output can drive series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of The PLL is ensured stable given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies from 25 MHz to 200 MHz. For normal operation, the external feedback input, FB_IN, is connected to one of the outputs. The internal VCO is running at multiples of the input reference clock set by the feedback divider Table 2, “Frequency Table,” on page When PLL_EN# is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. SELA PLL_EN REF_SEL TCLK PECL_CLK Phase Detector VCO 200 500 MHz FB_IN SELB SELC SELD QC0 QC1 QD0 QD1 QD2 QD3 QD4 • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Pinout Figure Pin Diagram - 32-Pin TQFP Package 32 REF_SEL 31 PLL_EN 30 TCLK 29 VSS 28 QA 27 VDDQB 26 QB 25 VSS AVDD FB_IN SELA SELB SELC SELD AVSS PECL_CLK 24 QC0 23 VDDQC 22 QC1 CY29351 21 20 VSS QD0 19 VDDQD 18 QD1 17 VSS CY29351 QD2 16 VDDQD 15 QD3 14 VSS 13 QD4 12 VDD 11 OE# 10 PECL_CLK# Table Pin Definitions - 32-Pin TQFP Package Pin[1] Ordering Information Part Number Pb-free CY29351AXI CY29351AXIT Package Type 32-pin TQFP 32-pin TQFP tape and reel Product Flow Industrial, to 85C Industrial, to 85C Page 8 of 10 [+] Feedback Package Drawing and Dimension Figure 32-Pin Thin Plastic Quad Flatpack 7 x 7 x mm CY29351 51-85063 *C Page 9 of 10 [+] Feedback CY29351 Document History Page Document Title CY29351 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer Document Number 38-07475 Orig. of Change Submission Date Description of Change 128152 07/07/2003 New Data Sheet 245448 See ECN Re-worded Select Function Descriptions in table 2001108 PYG/KVM/ AESA 01/23/2008 Corrected package thickness in Figure 7 from 1.4mm to 1.0mm. In Ordering Information, removed leaded and added Pb-free parts. 2675313 KVM/PYRS 03/17/2009 Removed ‘Preliminary’ status Corrected typo in Document History Page 3190648 03/08/2011 Updated the package diagram. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General psoc.cypress.com/solutions Low Power/Low Voltage psoc.cypress.com/low-power Precision Analog psoc.cypress.com/precision-analog LCD Drive psoc.cypress.com/lcd-drive CAN 2.0b psoc.cypress.com/can psoc.cypress.com/usb Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 10 of 10 [+] Feedback

PDF Datasheet Preview

CY29351
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
• Output Frequency Range 25 MHz to 200 MHz
• Input Frequency Range 25 MHz to 200 MHz
• 2.5V or 3.3V Operation
• Split 2.5V and 3.3V Outputs
• Max Output Duty Cycle Variation
• Nine Clock Outputs Drive up to 18 Clock Lines
• Two Reference Clock Inputs LVPECL or LVCMOS
• 150-ps Max Output-Output Skew
• Phase-locked Loop PLL Bypass Mode
• Spread Aware
• Output Enable or Disable
• Pin-compatible with MPC9351
• Industrial Temperature Range to +85°C
• 32-pin 1.0-mm TQFP Package

Logic Block Diagram

Functional Description

The CY29351 is a low voltage high performance 200 MHz PLL-based zero delay buffer designed for high speed clock distribution applications. The CY29351 features LVPECL and LVCMOS reference clock inputs and provides nine outputs partitioned in four banks of one, one, two, and five outputs. Bank A divides the VCO output by two or four while the other banks divide by four or eight per SEL A:D settings Table 3, “Function Table,” on page These dividers enable output to input ratios of 4:1, 2:1, 1:1, 1:2, and Each LVCMOS compatible output can drive series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of The PLL is ensured stable given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies from 25 MHz to 200 MHz. For normal operation, the external feedback input, FB_IN, is connected to one of the outputs. The internal VCO is running at multiples of the input reference clock set by the feedback divider Table 2, “Frequency Table,” on page When PLL_EN# is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply.

SELA PLL_EN

REF_SEL TCLK

PECL_CLK

Phase Detector

VCO 200 500 MHz

FB_IN SELB SELC

SELD

QC0 QC1

QD0 QD1 QD2 QD3 QD4
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Pinout

Figure Pin Diagram - 32-Pin TQFP Package
32 REF_SEL 31 PLL_EN 30 TCLK 29 VSS 28 QA 27 VDDQB 26 QB 25 VSS

AVDD FB_IN SELA SELB SELC SELD AVSS PECL_CLK
24 QC0
23 VDDQC
22 QC1

CY29351
21 20

VSS QD0
19 VDDQD
18 QD1
17 VSS

CY29351

QD2 16

VDDQD 15

QD3 14

VSS 13

QD4 12

VDD 11

OE# 10

PECL_CLK#

Table Pin Definitions - 32-Pin TQFP Package

Pin[1]
Ordering Information

Part Number Pb-free CY29351AXI CY29351AXIT

Package Type
32-pin TQFP 32-pin TQFP tape and reel

Product Flow

Industrial, to 85C Industrial, to 85C

Page 8 of 10 [+] Feedback

Package Drawing and Dimension

Figure 32-Pin Thin Plastic Quad Flatpack 7 x 7 x mm

CY29351
51-85063 *C

Page 9 of 10 [+] Feedback

CY29351

Document History Page

Document Title CY29351 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer Document Number 38-07475

Orig. of Change

Submission Date

Description of Change
128152
07/07/2003 New Data Sheet
245448

See ECN Re-worded Select Function Descriptions in table
2001108

PYG/KVM/ AESA
01/23/2008
Corrected package thickness in Figure 7 from 1.4mm to 1.0mm. In Ordering Information, removed leaded and added Pb-free parts.
2675313 KVM/PYRS
03/17/2009

Removed ‘Preliminary’ status Corrected typo in Document History Page
3190648
03/08/2011 Updated the package diagram.

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products PSoC Clocks & Buffers Wireless Memories Image Sensors
psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com

PSoC Solutions

General
psoc.cypress.com/solutions

Low Power/Low Voltage
psoc.cypress.com/low-power

Precision Analog
psoc.cypress.com/precision-analog

LCD Drive
psoc.cypress.com/lcd-drive

CAN 2.0b
psoc.cypress.com/can
psoc.cypress.com/usb

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

All products and company names mentioned in this document may be the trademarks of their respective holders.

Page 10 of 10
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY29351AXI Datasheet file may be downloaded here without warranties.

Datasheet ID: CY29351AXI 507738