CY28441ZXC

CY28441ZXC Datasheet

CY28441

Part	Datasheet
CY28441ZXC	CY28441ZXC (pdf)

Related Parts	Information
CY28441ZXCT	CY28441ZXCT

PDF Datasheet Preview
CY28441 Clock Generator for Alviso Chipset • Compliant to CK410M • Supports Intel CPU • Selectable CPU frequencies • Differential CPU clock pairs • 100-MHz differential SRC clocks • 96-MHz differential dot clock • 48-MHz USB clocks • SRC clocks independently stoppable through CLKREQ#[A:B] • 33-MHz PCI clock • Low-voltage frequency select input • I2C support with readback capabilities • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference EMI reduction • 3.3V power supply • 56-pin TSSOP package CPU SRC x2 / x3 x6 / x7 x 6 REF x1 DOT96 USB_48 Block Diagram XIN XOUT CPU_STP# PCI_STP# CLKREQ[A:B]# FS_[C:A] VTT_PWRGD# IREF XTAL OSC PLL Ref Freq PLL1 Divider Network PD PLL2 SDATA SCLK I2C Logic Pin Configuration VDD_REF REF VDD_PCI VSS_PCI VDD_CPU CPUT[0:1], CPUC[0:1], CPU T/C 2_ITP] VDD_SRC SRCT[0:5], SRCC[0:5] PCI3 PCI4 PCI5 VSS_PCI VDD_PCI PCIF0/ITP_EN PCIF1 VDD_PCI PCI[2:5] VTT_PWRGD#/PD VDD_48 VDD_PCIF PCIF[0:1] USB_48/FS_A VSS_48 DOT96T VDD_48 MHz DOT96C FS_B/TEST_MODE DOT96T DOT96C SRCT0 SRCC0 USB_48 Ordering Information Part Number Lead-free CY28441ZXC CY28441ZXCT Package Type 56-pin TSSOP 56-pin TSSOP Tape and Reel Product Flow Commercial, 0° to 85°C Commercial, 0° to 85°C Package Diagrams 56-Lead Thin Shrunk Small Outline Package, Type II 6 mm x 12 mm Z56 DIMENSIONS IN MM[INCHES] MIN. REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.42gms PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG. MAX. MAX. GAUGE PLANE SEATING PLANE 0° -8° 51-85060-*C Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Page 19 of 20 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback Document History Page Document Title CY28441 Clock Generator for Alviso Chipset Document Number 38-07679 Orig. of ECN NO. Issue Date Change 237792 See ECN RGL/SDR New Data Sheet Description of Change CY28441 Page 20 of 20 [+] Feedback

PDF Datasheet Preview

CY28441

Clock Generator for Alviso Chipset
• Compliant to CK410M
• Supports Intel CPU
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100-MHz differential SRC clocks
• 96-MHz differential dot clock
• 48-MHz USB clocks
• SRC clocks independently stoppable through

CLKREQ#[A:B]
• 33-MHz PCI clock
• Low-voltage frequency select input
• I2C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference EMI reduction
• 3.3V power supply
• 56-pin TSSOP package

CPU SRC
x2 / x3 x6 / x7 x 6

REF x1

DOT96 USB_48

Block Diagram

XIN XOUT

CPU_STP# PCI_STP# CLKREQ[A:B]#

FS_[C:A] VTT_PWRGD#

IREF

XTAL OSC

PLL Ref Freq

PLL1

Divider Network

PD PLL2

SDATA SCLK

I2C Logic

Pin Configuration

VDD_REF REF

VDD_PCI VSS_PCI

VDD_CPU

CPUT[0:1], CPUC[0:1], CPU T/C 2_ITP] VDD_SRC

SRCT[0:5], SRCC[0:5]

PCI3 PCI4 PCI5 VSS_PCI VDD_PCI

PCIF0/ITP_EN

PCIF1

VDD_PCI PCI[2:5]

VTT_PWRGD#/PD VDD_48

VDD_PCIF PCIF[0:1]

USB_48/FS_A VSS_48

DOT96T

VDD_48 MHz

DOT96C FS_B/TEST_MODE

DOT96T DOT96C

SRCT0 SRCC0

USB_48
Ordering Information

Part Number Lead-free CY28441ZXC CY28441ZXCT

Package Type
56-pin TSSOP 56-pin TSSOP Tape and Reel

Product Flow

Commercial, 0° to 85°C Commercial, 0° to 85°C

Package Diagrams
56-Lead Thin Shrunk Small Outline Package, Type II 6 mm x 12 mm Z56

DIMENSIONS IN MM[INCHES] MIN.

REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.42gms

PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG.

MAX.

MAX.

GAUGE PLANE

SEATING PLANE
0° -8°
51-85060-*C

Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

Page 19 of 20

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback

Document History Page

Document Title CY28441 Clock Generator for Alviso Chipset Document Number 38-07679

Orig. of ECN NO. Issue Date Change
237792 See ECN RGL/SDR New Data Sheet

Description of Change

CY28441

Page 20 of 20
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Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY28441ZXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY28441ZXC 507732