CY2304SC-2

CY2304SC-2 Datasheet


CY2304

Part Datasheet
CY2304SC-2 CY2304SC-2 CY2304SC-2 (pdf)
Related Parts Information
CY2304SI-1 CY2304SI-1 CY2304SI-1
CY2304SC-1 CY2304SC-1 CY2304SC-1
PDF Datasheet Preview
CY2304
3.3V Zero Delay Buffer
• Zero input-output propagation delay, adjustable by capacitive load on FBK input
• Multiple configurations see Table 1 on page 1
• Multiple low-skew outputs
• 10 MHz to 133 MHz operating range
• 90 ps typical peak cycle-to-cycle jitter at 15 pF, 66 MHz
• Space-saving 8-pin 150-mil SOIC package
• 3.3V operation
• Industrial temperature available

Functional Description

The CY2304 is a 3.3V zero delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip phase-locked loop PLL that locks to an input clock presented on the REF pin. The PLL feedback is
required to be driven into the FBK pin, and can be obtained from one of the outputs. The input-to-output skew is guaranteed to be less than 250 ps, and output-to-output skew is guaranteed to be less than 200 ps.

The CY2304 has two banks of two outputs each.

The CY2304 PLL enters a power down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off, resulting in less than 25 uA of current draw.

Multiple CY2304 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 500 ps.

The CY2304 is available in two different configurations, as shown in Table 1 on page The is the base part, where the output frequencies equal the reference if there is no counter in the feedback path.

The allows the user to obtain Ref and 1/2x or 2x frequencies on each output bank. The exact configuration and output frequencies depends on which output drives the feedback pin.

Logic Block Diagram

PLL REF

CLKA1 CLKA2

Extra Divider -2

CLKB1

Table Available Configurations

Device CY2304-1 CY2304-2 CY2304-2

FBK from Bank A or B

Bank A Bank B

Bank A Frequency Reference
2 x Reference

Pinouts

Figure 8-Pin SOIC - Top View

REF 1

CLKA1 2 CLKA2 3

GND 4
8 FBK 7 VDD 6 CLKB2
5 CLKB1

CLKB2

Bank B Frequency Reference/2 Reference
• San Jose, CA 95134-1709
• 408-943-2600
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CY2304

Table Pin Definitions - 8-Pin SOIC

Signal

REF[1]

CLKA1[2]

CLKA2[2]

CLKB1[2]
Ordering Information
Ordering Code Pb-Free

Test circuit for all parameters except t8

Package Type 8-pin 150-mil SOIC 8-pin 150-mil SOIC - Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC- Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC- Tape and Reel
8-pin 150-mil SOIC 8-pin 150-mil SOIC - Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC- Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC- Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC- Tape and Reel

Operating Range Commercial Industrial Commercial

Commercial Industrial Commercial Industrial

Note Not recommended for new designs.

Page 7 of 9 [+] Feedback

CY2304

Package Drawing and Dimensions
8 Lead 150 Mil SFOigICureS088. 8-Pin 150-Mil SOIC S8

PIN 1 ID

DIMENSIONS IN INCHES[MM] MIN.

MAX.

PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME

REFERENCE JEDEC MS-012 PACKAGE WEIGHT 0.07gms

PART # S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG.

SEATING PLANE

X 45°
0°~8°
51-85066-*C

Page 8 of 9 [+] Feedback

CY2304

Document History Page

Document Title CY2304 3.3V Zero Delay Buffer Document Number 38-07247

Orig. of Submission

Change

Description of Change
110512
12/11/01 Change from Spec number 38-01010 to 38-07247
112294
03/04/02 On Pin Configuration Diagram p.1 , swapped CLKA2 and CLKA1
113934
05/01/02 Added Operating Conditions for CY2304SI-X Industrial Temperature

Devices, p. 4
121851
12/14/02 Power up requirements added to Operating Conditions Information
308436
01/26/05 Added Lead-free Devices
2542331 AESA
09/18/08 Updated template. Added Note “Not recommended for new designs.”
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Datasheet ID: CY2304SC-2 507680