ATPL210A-A1U-Y

ATPL210A-A1U-Y Datasheet


Atmel ATPL210A

Part Datasheet
ATPL210A-A1U-Y ATPL210A-A1U-Y ATPL210A-A1U-Y (pdf)
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Atmel ATPL210A

PRIME compliant Power Line Communications SoC

SUMMARY DATASHEET
• Core
• ADD8051C3A enhanced 8051 core
• Speedups up to x5 vs. standard 8051 microcontroller
• Modem
• Power Line Carrier Modem for 50 and 60 Hz mains
• 97-carrier OFDM PRIME compliant
• Baud rate Selectable 21400 to 128600 bps
• Differential BPSK, QPSK, 8-PSK modulations
• Memories
• 32Kbytes on-chip SRAM
• Up to 256Kbytes external SRAM
• In-circuit serial flash programming
• Auto boot-loading program from serial flash
• Automatic Gain Control and signal amplitude tracking
• Embedded on-chip DMAs
• Automatic code encryption during boot loading
• Media Access Control
• Viterbi decoding and CRC PRIME compliant
• 128-bit AES encryption
• Channel sensing and collision pre-detection
• Peripherals
• Two 2-wire UARTs
• Two SPI. SPI to serial flash and External RTC. Buffered SPI to external metering

IC
• Programmable Watchdog
• Up to 14 I/O lines
• Package
• 120-lead LQFP, 14 x 14 mm, pitch mm
• Pb-free and RoHS compliant
• Typical Applications
• Automated Meter Reading AMR & Advanced Meter Management AMM
• Street lighting
• Home Automation
43003A-ATPL-03/12

The ATPL210 is a Power Line Communications System on Chip, which implements a full PRIME compliant PLC modem. It includes an enhanced 8051 microcontroller IP core ADD8051C3A , a Medium Access Controller MAC IP core ADD1221 and a Modem circuit IP core ADD1321 for power line medium using OFDM modulation compatible with PRIME specifications.

ATPL210 is oriented to high performance & robust AMR systems. The ATPL210 is designed to be used by meter manufacturers to provide a low cost and compact solution for AMR & AMM systems using narrow band power line communications.

This device has been developed to reduce CPU computational load in PLC systems running PRIME protocols. ATPL210 includes all necessary resources to be used as main controller in metering applications, and allows an external device to communicate according to PLC PRIME specifications.

Atmel ATPL210A [summary datasheet]
43003A-ATPL-03/12

Block Diagram

Figure ATPL210A 120-pin Block Diagram

DEBUG D_INIT

RSTA

CLKA CLKB

Reset Interface

Clock Interface
20MHz

RESET Clock

DEBUG
8051C3A Core

IDATA
32KB On-chip SRAM

P1.7 P3 0,1 P4 2:6 P5 0:5

VSENSE PSENSE EMIT 1:12 AFE_TXRX AFE_HIMP AGC0

VNR AGC1

VIN VRH VRL
Ordering Information
Table Atmel ATPL210A Ordering Codes
Atmel Ordering Code ATPL210A-A1U-Y

Package 120 LQFP

Package Type Pb-Free

Temperature Range Industrial -40ºC to 85º

Atmel Designator

AT=Atmel

Product Family

PL=Power Line Communications

Device Designator

ATPL210A-A1U-Yxx

Customer marking

Shipping Carrier Option

Y = Tray

Package Device Grade or Wafer/Die Thickness

U = Lead free Pb-free Industrial temperature range -40°C to +85°C

Package Option

A1 = 120LQFP

Atmel ATPL210A [summary datasheet]
43003A-ATPL-03/12

Date 30/03/2012

Comments Initial release

Atmel ATPL210A [summary datasheet]
43003A-ATPL-03/12

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Datasheet ID: ATPL210A-A1U-Y 519271