ADG528ATCHIPS

ADG528ATCHIPS Datasheet

ADG528A/ADG529A

Part	Datasheet
ADG528ATCHIPS	ADG528ATCHIPS (pdf)

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CMOS Latched 4-/8-Channel Analog Multiplexers ADG528A/ADG529A FEATURES 44 V Supply Maximum Rating VSS to VDD Analog Signal Range Single-/Dual-Supply Specifications Wide Supply Ranges V to V Microprocessor Compatible 100 ns WR Pulse Extended Plastic Temperature Range to +85°C Low Leakage 20 pA typ Low Power Dissipation 28 mW max Available in 18-Lead DIP/SOIC and 20-Lead PLCC Packages Superior Alternative to: DG528 DG529 FUNCTIONAL BLOCK DIAGRAMS GENERAL DESCRIPTION The ADG528A and ADG529A are CMOS monolithic analog multiplexers with eight channels and four dual channels, respectively. On-chip latches facilitate microprocessor interfacing. The ADG528A switches one of eight inputs to a common output, depending on the state of three binary addresses and an enable input. The ADG529A switches one of four differential inputs to a common differential output, depending on the state of two binary addresses and an enable input. Both devices have TTL and 5 V CMOS logic-compatible digital inputs. The ADG528A and ADG529A are designed on an enhanced LC2MOS process, which gives an increased signal capability of VSS to VDD and enables operation over a wide range of supply voltages. The devices can comfortably operate anywhere in the V to V single- or dual-supply range. These multiplexers also feature high switching and low RON. PRODUCT HIGHLIGHTS Single-/dual-supply specifications with a wide tolerance. The devices are specified in the V to V range for both single- and dual-supplies. Easily Interfaced The ADG528A and ADG529A can be easily interfaced with microprocessors. The WR signal latches the state of the address control lines and the enable line. The RS signal clears both the address and enable data in the latches resulting in no output all switches off . RS can be tied to the microprocessor reset pin. Extended Signal Range The enhanced LC2MOS processing results in a high breakdown and an increased analog signal range of VSS to VDD. Break-Before-Make Switching Switches are guaranteed break-before-make so that input signals are protected against momentary shorting. Low Leakage currents in the range of 20 pA make these multiplexers suitable for high precision circuits. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel 781/329-4700 Fax 781/326-8703 2004 Analog Devices, Inc. All rights reserved. DUAL SUPPLY VDD = V to V, VSS = V to V, unless otherwise noted. Parameter ADG528A ADG529A K Version to +25°C +85°C ADG528A ADG529A B Version to +25°C +85°C ADG528A ADG529A T Version to +25°C +125°C Units Comments ANALOG SWITCH Analog Signal Range RON Drift RON Match IS OFF , Off Input Leakage ID OFF , Off Input Leakage ADG528A ADG529A ID ON , On Channel Leakage ADG528A ADG529A IDIFF, Differential Off Output Leakage ADG529A only VSS VDD 280 ORDERING GUIDE Model Temperature Range Package Description Package Option1 ADG528AKN ADG528AKP-REEL ADG528ABQ ADG528ATQ ADG528ABCHIPS ADG528ATCHIPS to +85°C to +85°C to +85°C to +85°C to +125°C PDIP PLCC CERDIP DIE N-18 P-20A P-20A Q-18 Q-18 ADG529AKN ADG529AKP ADG529AKRW-REEL ADG529AKRW-REEL7 ADG529ABQ ADG529ATQ ADG529ABCHIPS ADG529ATCHIPS to +85°C to +85°C to +85°C to +85°C to +85°C to +85°C to +125°C PDIP PLCC SOIC CERDIP DIE N-18 P-20A RW-18 RW-18 RW-18 Q-18 Q-18 NOTES 1N = Plastic DIP P = Plastic Leaded Chip Carrier PLCC Q = Cerdip RW = SOIC. CAUTION ESD electrostatic discharge sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG528A/ADG529A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ADG528A/ADG529A TRUTH TABLES A2 A1 A0 EN WR RS ON SWITCH PAIR XXXX X XXX0 0 0001 0 0011 0 0101 0 0111 0 1001 0 1011 0 1101 0 1111 0 1 Retains Previous Switch Condition 0 NONE Address and Enable Latches Cleared 1 NONE 11 12 13 14 15 16 17 18 X = Don’t Care ADG528A A1 A0 EN WR RS ON SWITCH PAIR 1 Retains Previous Switch Condition X 0 NONE Address and Enable Latches Cleared X 0 1 NONE 001 0 1 011 0 1 2 101 0 1 3 111 0 1 4 X = Don’t Care ADG529A TIMING DIAGRAMS Figure Figure 1 shows the timing sequence for latching the switch address and enable inputs. The latches are level sensitive therefore, while WR is held low, the latches are transparent and the switches respond to the address and enable inputs. This input data is latched on the rising edge of WR. Figure 2 shows the Reset Pulse Width, tRS, and Reset Turn-off Time, tOFF RS . Note All digital input signals rise and fall times measured from 10% to 90% of 3 V. tR = tF = 20 ns. Typical Performance Changes to ORDERING GUIDE 6 SOIC added to DIP PIN CONFIGURATION 5 Updated OUTLINE DIMENSIONS 9

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CMOS Latched 4-/8-Channel Analog Multiplexers

ADG528A/ADG529A

FEATURES 44 V Supply Maximum Rating VSS to VDD Analog Signal Range Single-/Dual-Supply Specifications Wide Supply Ranges V to V Microprocessor Compatible 100 ns WR Pulse Extended Plastic Temperature Range
to +85°C Low Leakage 20 pA typ Low Power Dissipation 28 mW max Available in 18-Lead DIP/SOIC and 20-Lead PLCC Packages Superior Alternative to:

DG528 DG529

FUNCTIONAL BLOCK DIAGRAMS

GENERAL DESCRIPTION The ADG528A and ADG529A are CMOS monolithic analog multiplexers with eight channels and four dual channels, respectively. On-chip latches facilitate microprocessor interfacing. The ADG528A switches one of eight inputs to a common output, depending on the state of three binary addresses and an enable input. The ADG529A switches one of four differential inputs to a common differential output, depending on the state of two binary addresses and an enable input. Both devices have TTL and 5 V CMOS logic-compatible digital inputs.

The ADG528A and ADG529A are designed on an enhanced LC2MOS process, which gives an increased signal capability of VSS to VDD and enables operation over a wide range of supply voltages. The devices can comfortably operate anywhere in the V to V single- or dual-supply range. These multiplexers also feature high switching and low RON.

PRODUCT HIGHLIGHTS Single-/dual-supply specifications with a wide tolerance.

The devices are specified in the V to V range for both single- and dual-supplies.

Easily Interfaced The ADG528A and ADG529A can be easily interfaced with microprocessors. The WR signal latches the state of the address control lines and the enable line. The RS signal clears both the address and enable data in the latches resulting in no output all switches off . RS can be tied to the microprocessor reset pin.

Extended Signal Range The enhanced LC2MOS processing results in a high breakdown and an increased analog signal range of VSS to VDD.

Break-Before-Make Switching Switches are guaranteed break-before-make so that input signals are protected against momentary shorting.

Low Leakage currents in the range of 20 pA make these multiplexers suitable for high precision circuits.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel 781/329-4700

Fax 781/326-8703 2004 Analog Devices, Inc. All rights reserved.

DUAL SUPPLY VDD = V to V, VSS = V to V, unless otherwise noted.

Parameter

ADG528A

ADG529A

K Version to
+25°C +85°C

ADG528A

ADG529A

B Version to
+25°C +85°C

ADG528A

ADG529A

T Version to
+25°C +125°C

Units

Comments

ANALOG SWITCH Analog Signal Range

RON Drift RON Match IS OFF , Off Input

Leakage

ID OFF , Off Input Leakage ADG528A ADG529A

ID ON , On Channel Leakage ADG528A ADG529A

IDIFF, Differential Off Output Leakage ADG529A only

VSS VDD 280
ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option1

ADG528AKN ADG528AKP-REEL ADG528ABQ ADG528ATQ ADG528ABCHIPS ADG528ATCHIPS
to +85°C to +85°C to +85°C to +85°C to +125°C

PDIP PLCC CERDIP DIE

N-18 P-20A P-20A Q-18 Q-18

ADG529AKN ADG529AKP ADG529AKRW-REEL ADG529AKRW-REEL7 ADG529ABQ ADG529ATQ ADG529ABCHIPS ADG529ATCHIPS
to +85°C to +85°C to +85°C to +85°C to +85°C to +85°C to +125°C

PDIP PLCC SOIC CERDIP DIE

N-18 P-20A RW-18 RW-18 RW-18 Q-18 Q-18

NOTES 1N = Plastic DIP P = Plastic Leaded Chip Carrier PLCC Q = Cerdip RW = SOIC.

CAUTION ESD electrostatic discharge sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG528A/ADG529A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ADG528A/ADG529A

TRUTH TABLES

A2 A1 A0 EN WR RS ON SWITCH PAIR

XXXX X

XXX0 0 0001 0 0011 0 0101 0 0111 0 1001 0 1011 0 1101 0 1111 0
1 Retains Previous Switch Condition 0 NONE Address and Enable

Latches Cleared 1 NONE 11 12 13 14 15 16 17 18

X = Don’t Care

ADG528A

A1 A0 EN WR RS ON SWITCH PAIR
1 Retains Previous Switch Condition

X 0 NONE Address and Enable Latches

Cleared

X 0 1 NONE
001 0 1
011 0 1 2
101 0 1 3
111 0 1 4

X = Don’t Care

ADG529A

TIMING DIAGRAMS

Figure

Figure 1 shows the timing sequence for latching the switch address and enable inputs. The latches are level sensitive therefore, while WR is held low, the latches are transparent and the switches respond to the address and enable inputs. This input data is latched on the rising edge of WR. Figure 2 shows the Reset Pulse Width, tRS, and Reset Turn-off Time, tOFF RS . Note All digital input signals rise and fall times measured from 10% to 90% of 3 V. tR = tF = 20 ns.

Typical Performance
Changes to ORDERING GUIDE 6

SOIC added to DIP PIN CONFIGURATION 5

Updated OUTLINE DIMENSIONS 9

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Datasheet ID: ADG528ATCHIPS 517817