CYP15G0101DXB-BBC

CYP15G0101DXB-BBC Datasheet

CYP15G0101DXB CYV15G0101DXB

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CYP15G0101DXB-BBC	CYP15G0101DXB-BBC (pdf)

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CYP15G0101DXB CYV15G0101DXB Single-channel HOTLink II Transceiver Single-channel HOTLink II Transceiver • Second-generation technology • Compliant to multiple standards DVB-ASI, fibre channel and gigabit ethernet IEEE802.3z CPRI compliant CYV15G0101DXB compliant to SMPTE 259M and SMPTE 292M 8B/10B encoded or 10-bit unencoded data • Single-channel transceiver operates from 195 to 1500 MBaud serial data rate • Selectable parity check/generate • Selectable input clocking options • Selectable output clocking options • MultiFrame Receive Framer Bit and byte alignment Comma or full K28.5 detect Single- or multi-byte framer for byte alignment Low-latency option • Synchronous LVTTL parallel input and parallel output interface • Internal phase-locked loops PLLs with no external PLL components • Dual differential PECL-compatible serial inputs Internal DC-restoration • Dual differential PECL-compatible serial outputs Source matched for driving 50 Ω transmission lines No external bias resistors required Signaling-rate controlled edge-rates • Optional elasticity buffer in receive path • Optional phase align buffer in transmit path • Compatible with Fiber-optic modules Copper cables Circuit board traces • JTAG boundary scan • Built-in self-test BIST for at-speed link testing • Per-channel link quality indicator Analog signal detect Digital signal detect • Low power W at V typical • Single V supply • 100-ball BGA • Pb-free package option available • µ BiCMOS technology Functional Description The CYP15G0101DXB[1] single-channel HOTLink II transceiver is a point-to-point communications building block allowing the transfer of data over a high-speed serial link optical fiber, balanced, and unbalanced copper transmission lines at signaling speeds ranging from 195 to 1500 MBaud. The transmit channel accepts parallel characters in an input register, encodes each character for transport, and converts it to serial data. The receive channel accepts serial data and converts it to parallel data, frames the data to character boundaries, decodes the framed characters into data and special characters, and presents these characters to an output register. Figure 1 illustrates typical connections between independent host systems and corresponding CYP V 15G0101DXB parts. As a second-generation HOTLink device, the CYP V 15G0101DXB extends the HOTLink II family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility data, command, and BIST with other HOTLink devices. Figure HOTLink II System Connections Serial Link Backplane or Cabled Connections System Host CYP V 15G0101DXB CYP V 15G0101DXB System Host Note CYV15G0101DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYP15G0101DXB refers to devices not compliant to SMPTE 259M and SMPTE 292M pathological test requirements. CYP V 15G0101DXB refers both devices. • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CYP15G0101DXB CYV15G0101DXB The CYV15G0101DXB satisfies the SMPTE 259M and SMPTE 292M compliance as per the EG34-1999 pathological test requirements. The transmit TX section of the CYP V 15G0101DXB single-channel HOTLink II consists of a byte-wide channel. The channel can accept either eight-bit data characters or pre-encoded 10-bit transmission characters. Data characters are passed from the transmit input register to an embedded 8B/10B encoder to improve their serial transmission characteristics. These encoded characters are then serialized and output from dual positive ECL PECL -compatible differential transmission-line drivers at a bit-rate of either 10 or 20 times the input reference clock. The receive RX section of the CYP V 15G0101DXB single-channel HOTLink II consists of a byte-wide channel. The channel accepts a serial bit-stream from one of two PECL-compatible differential line receivers and, using a completely integrated PLL clock synchronizer, recovers the timing information necessary for data reconstruction. The recovered bit-stream is deserialized and framed into characters, 8B/10B decoded, and checked for transmission errors. Recovered decoded characters are then written to an internal elasticity buffer, and presented to the destination host system. The integrated 8B/10B encoder/decoder may be bypassed for systems that present externally encoded or scrambled data at the parallel interface. The parallel I/O interface may be configured for numerous forms of clocking to provide the highest flexibility in system architecture. In addition to clocking the transmit path interfaces from one or multiple sources, the receive interface may be configured to present data relative to a recovered clock or to a local reference clock. Notation Conventions 33 8B/10B Transmission Code 33 Transmission Order 33 Valid and Invalid Transmission Characters 33 Use of the Tables for Generating Transmission Characters 34 Use of the Tables for Checking the Validity of Received Transmission Characters 34 Ordering Information 40 Ordering Code Definitions 40 Package Diagram 41 Acronyms 42 Document Conventions 42 Document History Page 43 Sales, Solutions, and Legal Information 44 Worldwide Sales and Design Support 44 Products 44 PSoC Solutions 44 Page 4 of 44 [+] Feedback CYP15G0101DXB CYV15G0101DXB Pin Configuration Top View IN2+ RXMODE TXMODE[1] IN1+ OUT2+ TXRATE TXMODE[0] #NC[2] OUT1+ RFEN LPEN RXLE RXCLKC+ RXRATE SDASEL SPDSEL PARCTL RFMODE INSEL BOE[0] BOE[1] FRAMCHAR GND TRSTZ BISTLE DECMODE OELE TCLK RXCKSEL TXCKSEL RXST[2] RXST[1] RXST[0] GND TXPER REFCLK+ RXOP RXD[1] RXD[5] TXOP TXCLKO+ RXD[0] RXD[2] RXD[6] TXCT[1] TXD[6] TXD[3] TXCLK TXRST #NC[2] RXD[3] RXD[7] TXCT[0] TXD[5] TXD[2] TXD[0] #NC[2] RXD[4] RXCLK+ TXD[7] TXD[4] TXD[1] SCSEL Bottom View IN1+ TXMODE[1] RXMODE IN2+ OUT1+ #NC[2] TXMODE[0] TXRATE OUT2+ INSEL RFMODE PARCTL SPDSEL SDASEL RXRATE RXCLKC+ RXLE LPEN RFEN The following information describes how the tables are used for both generating valid Transmission Characters encoding and checking the validity of received Transmission Characters decoding . It also specifies the ordering rules to be followed when transmitting the bits within a character and the characters within any higher-level constructs specified by a standard. Transmission Order Within the definition of the 8B/10B Transmission Code, the bit positions of the Transmission Characters are labeled a, b, c, d, e, i, f, g, h, j. Bit “a” is transmitted first followed by bits b, c, d, e, i, f, g, h, and j in that order. Note that bit i is transmitted between bit e and bit f, rather than in alphabetical order. Valid and Invalid Transmission Characters The following tables define the valid Data Characters and valid Special Characters K characters , respectively. The tables are used for both generating valid Transmission Characters and checking the validity of received Transmission Characters. In the tables, each Valid-Data-byte or Special-Character-code entry has two columns that represent two Transmission Characters. The two columns correspond to the current value of the running disparity. Running disparity is a binary parameter with either a negative or positive + value. After powering on, the Transmitter may assume either a positive or negative value for its initial running disparity. Upon transmission of any Transmission Character, the transmitter will select the proper version of the Transmission Character based on the current running disparity value, and the Transmitter Page 33 of 44 [+] Feedback CYP15G0101DXB CYV15G0101DXB calculates a new value for its running disparity based on the contents of the transmitted character. Special Character codes C1.7 and C2.7 can be used to force the transmission of a specific Special Character with a specific running disparity as required for some special sequences in X3.230. After powering on, the Receiver may assume either a positive or negative value for its initial running disparity. Upon reception of any Transmission Character, the Receiver decides whether the Transmission Character is valid or invalid according to the following rules and tables and calculates a new value for its Running Disparity based on the contents of the received character. The following rules for running disparity are used to calculate the new running-disparity value for Transmission Characters that have been transmitted Transmitter’s running disparity and that have been received Receiver’s running disparity . Running disparity for a Transmission Character is calculated from sub-blocks, where the first six bits abcdei form one sub-block and the second four bits fghj form the other sub-block. Running disparity at the beginning of the six-bit sub-block is the running disparity at the end of the previous Transmission Character. Running disparity at the beginning of the four-bit sub-block is the running disparity at the end of the six-bit sub-block. Running disparity at the end of the Transmission Character is the running disparity at the end of the four-bit sub-block. Running disparity for the sub-blocks is calculated as follows: Running disparity at the end of any sub-block is positive if the sub-block contains more ones than zeros. It is also positive at the end of the six-bit sub-block if the six-bit sub-block is 000111, and it is positive at the end of the four-bit sub-block if the four-bit sub-block is Running disparity at the end of any sub-block is negative if the sub-block contains more zeros than ones. It is also negative at the end of the six-bit sub-block if the six-bit sub-block is 111000, and it is negative at the end of the four-bit sub-block if the four-bit sub-block is Otherwise, running disparity at the end of the sub-block is the same as at the beginning of the sub-block. disparity is calculated. This new value is used as the Transmitter’s current running disparity for the next Valid Data byte or Special Character byte to be encoded and transmitted. Table 18 shows naming notations and examples of valid transmission characters. Use of the Tables for Checking the Validity of Received Transmission Characters The column corresponding to the current value of the Receiver’s running disparity is searched for the received Transmission Character. If the received Transmission Character is found in the proper column, then the Transmission Character is valid and the Data byte or Special Character code is determined decoded . If the received Transmission Character is not found in that column, then the Transmission Character is invalid. This is called a code violation. Independent of the Transmission Character’s validity, the received Transmission Character is used to calculate a new value of running disparity. The new value is used as the Receiver’s current running disparity for the next received Transmission Character. Table Valid Transmission Characters Byte Name Data DIN or QOUT 765 43210 Hex Value D0.0 D1.0 000 00001 D2.0 000 00010 D5.2 010 00101 D30.7 111 11110 Use of the Tables for Generating Transmission Characters The appropriate entry in the table is found for the Valid Data byte or the Special Character byte for which a Transmission Character is to be generated encoded . The current value of the Transmitter’s running disparity is used to select the Transmission Character from its corresponding column. For each Transmission Character transmitted, a new value of the running D31.7 Detection of a code violation does not necessarily show that the Transmission Character in which the code violation was detected is in error. Code violations may result from a prior error that altered the running disparity of the bit stream which did not result in a detectable error at the Transmission Character in which the error occurred. Table 19 shows an example of this behavior. Table Code Violations Resulting from Prior Errors Character Character Ordering Information Speed Standard Ordering Code CYP15G0101DXB-BBC CYP15G0101DXB-BBXC CYP15G0101DXB-BBXI CYV15G0101DXB-BBXC Package Name BB100 Ordering Code Definitions CY X15G0101 DXB - BB X Package Type 100-ball Grid Array Pb-free 100-ball Grid Array Pb-free 100-ball Grid Array Pb-free 100-ball Grid Array Operating Range Commercial Industrial Commercial X = Temperature Grade = C or I C = Commercial I = Industrial X = Pb-free BB = 100-ball BGA Fixed Value Part Identifier Company ID CY = Cypress Page 40 of 44 [+] Feedback CYP15G0101DXB CYV15G0101DXB Package Diagram Figure 100-ball Thin Ball Grid Array 11 x 11 x mm BB100 51-85107 *C Page 41 of 44 [+] Feedback CYP15G0101DXB CYV15G0101DXB Acronyms The following table lists the acronyms that are used in this document. Table Acronyms Used in this Datasheet Acronym BGA BIST I/O JTAG PLL TMS TDO TDI Description ball grid array built-in self test input/output joint test action group phase-locked loop test mode select test data out test data in Document Conventions Table Units of Measure Acronym °C kΩ µA µs mA ms mV nA Ω pF V W Description degree Celsius Kilo ohm micro Amperes micro second milli Amperes milli second milli Volts nano Amperes ohm pico Farad Volts Watts Page 42 of 44 [+] Feedback CYP15G0101DXB CYV15G0101DXB Document History Page Document Title CYP15G0101DXB/CYV15G0101DXB Single-channel HOTLink II Transceiver Document Number 38-02031 Submission Orig. of Change Description of Change 113123 05/20/02 TPS New Data Sheet 119704 10/30/02 LNM Changed TXPER description Changed TXCLKO description Changed RXCKSEL to include RXCLKC+ Removed disparity reference from RFMODE Removed the LOW setting for FRAMCHAR and related references Removed references to ATM transport Changed the IOST boundary values Changed VODIF and VOLC for CML output Changed the tTXCLKR and tTXCLKF min. values Changed tTXDS, tTXDH, tTREFDS, and tTREFDH Changed and tREFCDV+ Changed the JTAG ID from 0C804069 to 1C804069 Added a section for characterization and standards compliance Changed I/O type of RXCLKC in I/O coordinates table 122209 12/28/02 RBI Minor Change Document Control corrected Document History Page 2898355 03/24/2010 CGX Removed inactive parts from Ordering Information. Updated Packaging Information. Page 43 of 44 [+] Feedback CYP15G0101DXB CYV15G0101DXB Document Title CYP15G0101DXB/CYV15G0101DXB Single-channel HOTLink II Transceiver Document Number 38-02031 Submission Orig. of Change Description of Change 3053045 10/08/2010 CGX Updated Ordering Information and added Ordering Code Definitions. Added Acronyms and Document Conventions. Minor edits and updated in new template. 3243269 04/28/2011 SAAC Removed the following part numbers from the Ordering Information on page 40 since the parts are no longer active. CDT 98703 a CYP15G0101DXB-BBI b CYV15G0101DXB-BBI c CYW15G0101DXB-BBXI Removed all references to the part CYW15G0101DXB from the datasheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 44 of 44 HOTLink is a registered trademark, and HOTLink II and MultiFrame are trademarks, of Cypress Semiconductor Corporation. CPRI is a trademark of Siemens AG. IBM and ESCON are registered trademarks, and FICON is a trademark, of International Business Machines. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback

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CYP15G0101DXB CYV15G0101DXB

Single-channel HOTLink II Transceiver

Single-channel HOTLink II Transceiver
• Second-generation technology
• Compliant to multiple standards DVB-ASI, fibre channel and gigabit ethernet IEEE802.3z CPRI compliant CYV15G0101DXB compliant to SMPTE 259M and SMPTE 292M 8B/10B encoded or 10-bit unencoded data
• Single-channel transceiver operates from 195 to 1500 MBaud serial data rate
• Selectable parity check/generate
• Selectable input clocking options
• Selectable output clocking options
• MultiFrame Receive Framer Bit and byte alignment Comma or full K28.5 detect Single- or multi-byte framer for byte alignment Low-latency option
• Synchronous LVTTL parallel input and parallel output interface
• Internal phase-locked loops PLLs with no external PLL components
• Dual differential PECL-compatible serial inputs Internal DC-restoration
• Dual differential PECL-compatible serial outputs Source matched for driving 50 Ω transmission lines No external bias resistors required Signaling-rate controlled edge-rates
• Optional elasticity buffer in receive path
• Optional phase align buffer in transmit path
• Compatible with Fiber-optic modules Copper cables Circuit board traces
• JTAG boundary scan
• Built-in self-test BIST for at-speed link testing
• Per-channel link quality indicator Analog signal detect Digital signal detect
• Low power W at V typical
• Single V supply
• 100-ball BGA
• Pb-free package option available
• µ BiCMOS technology

Functional Description

The CYP15G0101DXB[1] single-channel HOTLink II transceiver is a point-to-point communications building block allowing the transfer of data over a high-speed serial link optical fiber, balanced, and unbalanced copper transmission lines at signaling speeds ranging from 195 to 1500 MBaud.

The transmit channel accepts parallel characters in an input register, encodes each character for transport, and converts it to serial data. The receive channel accepts serial data and converts it to parallel data, frames the data to character boundaries, decodes the framed characters into data and special characters, and presents these characters to an output register. Figure 1 illustrates typical connections between independent host systems and corresponding CYP V 15G0101DXB parts. As a second-generation HOTLink device, the CYP V 15G0101DXB extends the HOTLink II family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility data, command, and BIST with other HOTLink devices.

Figure HOTLink II System Connections

Serial Link

Backplane or Cabled Connections

System Host CYP V 15G0101DXB CYP V 15G0101DXB

System Host

Note

CYV15G0101DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYP15G0101DXB refers to devices not compliant to SMPTE 259M and SMPTE 292M pathological test requirements. CYP V 15G0101DXB refers both devices.
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CYP15G0101DXB CYV15G0101DXB

The CYV15G0101DXB satisfies the SMPTE 259M and SMPTE 292M compliance as per the EG34-1999 pathological test requirements. The transmit TX section of the CYP V 15G0101DXB single-channel HOTLink II consists of a byte-wide channel. The channel can accept either eight-bit data characters or pre-encoded 10-bit transmission characters. Data characters are passed from the transmit input register to an embedded 8B/10B encoder to improve their serial transmission characteristics. These encoded characters are then serialized and output from dual positive ECL PECL -compatible differential transmission-line drivers at a bit-rate of either 10 or 20 times the input reference clock.

The receive RX section of the CYP V 15G0101DXB single-channel HOTLink II consists of a byte-wide channel. The channel accepts a serial bit-stream from one of two PECL-compatible differential line receivers and, using a completely integrated PLL clock synchronizer, recovers the timing information necessary for data reconstruction. The recovered bit-stream is deserialized and framed into characters, 8B/10B decoded, and checked for transmission errors. Recovered decoded characters are then written to an internal elasticity buffer, and presented to the destination host system. The integrated 8B/10B encoder/decoder may be bypassed for systems that present externally encoded or scrambled data at the parallel interface.

The parallel I/O interface may be configured for numerous forms of clocking to provide the highest flexibility in system architecture. In addition to clocking the transmit path interfaces from one or multiple sources, the receive interface may be configured to present data relative to a recovered clock or to a local reference clock.
Notation Conventions 33 8B/10B Transmission Code 33 Transmission Order 33 Valid and Invalid Transmission Characters 33 Use of the Tables for Generating Transmission Characters 34 Use of the Tables for Checking the Validity of Received Transmission Characters 34 Ordering Information 40 Ordering Code Definitions 40 Package Diagram 41 Acronyms 42 Document Conventions 42 Document History Page 43 Sales, Solutions, and Legal Information 44 Worldwide Sales and Design Support 44 Products 44 PSoC Solutions 44

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CYP15G0101DXB CYV15G0101DXB

Pin Configuration

Top View

IN2+

RXMODE TXMODE[1] IN1+

OUT2+ TXRATE TXMODE[0]
#NC[2] OUT1+

RFEN

LPEN

RXLE RXCLKC+ RXRATE SDASEL SPDSEL PARCTL RFMODE INSEL

BOE[0] BOE[1] FRAMCHAR GND

TRSTZ

BISTLE DECMODE OELE

TCLK RXCKSEL TXCKSEL

RXST[2] RXST[1] RXST[0] GND

TXPER REFCLK+

RXOP RXD[1] RXD[5]

TXOP TXCLKO+

RXD[0] RXD[2] RXD[6]

TXCT[1] TXD[6]

TXD[3]

TXCLK TXRST #NC[2]

RXD[3]

RXD[7] TXCT[0] TXD[5]

TXD[2]

TXD[0]
#NC[2]

RXD[4]

RXCLK+ TXD[7] TXD[4] TXD[1]

SCSEL

Bottom View

IN1+ TXMODE[1] RXMODE

IN2+

OUT1+
#NC[2]

TXMODE[0] TXRATE OUT2+

INSEL RFMODE PARCTL SPDSEL SDASEL RXRATE RXCLKC+ RXLE

LPEN

RFEN
The following information describes how the tables are used for both generating valid Transmission Characters encoding and checking the validity of received Transmission Characters decoding . It also specifies the ordering rules to be followed when transmitting the bits within a character and the characters within any higher-level constructs specified by a standard.

Transmission Order

Within the definition of the 8B/10B Transmission Code, the bit positions of the Transmission Characters are labeled a, b, c, d, e, i, f, g, h, j. Bit “a” is transmitted first followed by bits b, c, d, e, i, f, g, h, and j in that order.

Note that bit i is transmitted between bit e and bit f, rather than in alphabetical order.

Valid and Invalid Transmission Characters

The following tables define the valid Data Characters and valid Special Characters K characters , respectively. The tables are used for both generating valid Transmission Characters and checking the validity of received Transmission Characters. In the tables, each Valid-Data-byte or Special-Character-code entry has two columns that represent two Transmission Characters. The two columns correspond to the current value of the running disparity. Running disparity is a binary parameter with either a negative or positive + value.

After powering on, the Transmitter may assume either a positive or negative value for its initial running disparity. Upon transmission of any Transmission Character, the transmitter will select the proper version of the Transmission Character based on the current running disparity value, and the Transmitter

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CYP15G0101DXB CYV15G0101DXB
calculates a new value for its running disparity based on the contents of the transmitted character. Special Character codes C1.7 and C2.7 can be used to force the transmission of a specific Special Character with a specific running disparity as required for some special sequences in X3.230.

After powering on, the Receiver may assume either a positive or negative value for its initial running disparity. Upon reception of any Transmission Character, the Receiver decides whether the Transmission Character is valid or invalid according to the following rules and tables and calculates a new value for its Running Disparity based on the contents of the received character.

The following rules for running disparity are used to calculate the new running-disparity value for Transmission Characters that have been transmitted Transmitter’s running disparity and that have been received Receiver’s running disparity .

Running disparity for a Transmission Character is calculated from sub-blocks, where the first six bits abcdei form one sub-block and the second four bits fghj form the other sub-block. Running disparity at the beginning of the six-bit sub-block is the running disparity at the end of the previous Transmission Character. Running disparity at the beginning of the four-bit sub-block is the running disparity at the end of the six-bit sub-block. Running disparity at the end of the Transmission Character is the running disparity at the end of the four-bit sub-block.

Running disparity for the sub-blocks is calculated as follows:

Running disparity at the end of any sub-block is positive if the sub-block contains more ones than zeros. It is also positive at the end of the six-bit sub-block if the six-bit sub-block is 000111, and it is positive at the end of the four-bit sub-block if the four-bit sub-block is

Running disparity at the end of any sub-block is negative if the sub-block contains more zeros than ones. It is also negative at the end of the six-bit sub-block if the six-bit sub-block is 111000, and it is negative at the end of the four-bit sub-block if the four-bit sub-block is

Otherwise, running disparity at the end of the sub-block is the same as at the beginning of the sub-block.
disparity is calculated. This new value is used as the Transmitter’s current running disparity for the next Valid Data byte or Special Character byte to be encoded and transmitted. Table 18 shows naming notations and examples of valid transmission characters.

Use of the Tables for Checking the Validity of Received Transmission Characters

The column corresponding to the current value of the Receiver’s running disparity is searched for the received Transmission Character. If the received Transmission Character is found in the proper column, then the Transmission Character is valid and the Data byte or Special Character code is determined decoded . If the received Transmission Character is not found in that column, then the Transmission Character is invalid. This is called a code violation. Independent of the Transmission Character’s validity, the received Transmission Character is used to calculate a new value of running disparity. The new value is used as the Receiver’s current running disparity for the next received Transmission Character.

Table Valid Transmission Characters

Byte Name

Data DIN or QOUT 765 43210

Hex Value

D0.0

D1.0
000 00001

D2.0
000 00010

D5.2
010 00101

D30.7
111 11110

Use of the Tables for Generating Transmission Characters

The appropriate entry in the table is found for the Valid Data byte or the Special Character byte for which a Transmission Character is to be generated encoded . The current value of the Transmitter’s running disparity is used to select the Transmission Character from its corresponding column. For each Transmission Character transmitted, a new value of the running

D31.7

Detection of a code violation does not necessarily show that the Transmission Character in which the code violation was detected is in error. Code violations may result from a prior error that altered the running disparity of the bit stream which did not result in a detectable error at the Transmission Character in which the error occurred. Table 19 shows an example of this behavior.

Table Code Violations Resulting from Prior Errors

Character

Character
Ordering Information

Speed Standard
Ordering Code CYP15G0101DXB-BBC CYP15G0101DXB-BBXC CYP15G0101DXB-BBXI CYV15G0101DXB-BBXC

Package Name BB100
Ordering Code Definitions CY X15G0101 DXB - BB X

Package Type 100-ball Grid Array Pb-free 100-ball Grid Array Pb-free 100-ball Grid Array Pb-free 100-ball Grid Array

Operating Range Commercial Industrial Commercial

X = Temperature Grade = C or I C = Commercial I = Industrial X = Pb-free BB = 100-ball BGA Fixed Value Part Identifier Company ID CY = Cypress

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CYP15G0101DXB CYV15G0101DXB

Package Diagram

Figure 100-ball Thin Ball Grid Array 11 x 11 x mm BB100
51-85107 *C

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CYP15G0101DXB CYV15G0101DXB

Acronyms

The following table lists the acronyms that are used in this document.

Table Acronyms Used in this Datasheet

Acronym BGA BIST I/O JTAG PLL TMS TDO TDI

Description ball grid array built-in self test input/output joint test action group phase-locked loop test mode select test data out test data in

Document Conventions

Table Units of Measure

Acronym °C kΩ µA µs mA ms mV nA Ω pF V W

Description degree Celsius Kilo ohm micro Amperes micro second milli Amperes milli second milli Volts nano Amperes ohm pico Farad Volts Watts

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CYP15G0101DXB CYV15G0101DXB

Document History Page

Document Title CYP15G0101DXB/CYV15G0101DXB Single-channel HOTLink II Transceiver Document Number 38-02031

Submission Orig. of

Change

Description of Change
113123 05/20/02

TPS New Data Sheet
119704 10/30/02

LNM Changed TXPER description

Changed TXCLKO description

Changed RXCKSEL to include RXCLKC+

Removed disparity reference from RFMODE

Removed the LOW setting for FRAMCHAR and related references

Removed references to ATM transport

Changed the IOST boundary values Changed VODIF and VOLC for CML output Changed the tTXCLKR and tTXCLKF min. values Changed tTXDS, tTXDH, tTREFDS, and tTREFDH Changed and tREFCDV+ Changed the JTAG ID from 0C804069 to 1C804069

Added a section for characterization and standards compliance

Changed I/O type of RXCLKC in I/O coordinates table
122209 12/28/02

RBI Minor Change Document Control corrected Document History Page
2898355 03/24/2010 CGX Removed inactive parts from Ordering Information.

Updated Packaging Information.

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CYP15G0101DXB CYV15G0101DXB

Document Title CYP15G0101DXB/CYV15G0101DXB Single-channel HOTLink II Transceiver Document Number 38-02031

Submission Orig. of

Change

Description of Change
3053045 10/08/2010 CGX Updated Ordering Information and added Ordering Code Definitions.

Added Acronyms and Document Conventions.

Minor edits and updated in new template.
3243269 04/28/2011 SAAC Removed the following part numbers from the Ordering Information on page 40
since the parts are no longer active. CDT 98703
a CYP15G0101DXB-BBI
b CYV15G0101DXB-BBI
c CYW15G0101DXB-BBXI

Removed all references to the part CYW15G0101DXB from the datasheet

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Datasheet ID: CYP15G0101DXB-BBC 507653