CY7C1520AV18-250BZC

CY7C1520AV18-250BZC Datasheet

CY7C1518AV18 CY7C1520AV18

Part	Datasheet
CY7C1520AV18-250BZC	CY7C1520AV18-250BZC (pdf)

Related Parts	Information
CY7C1518AV18-167BZC	CY7C1518AV18-167BZC
CY7C1518AV18-250BZC	CY7C1518AV18-250BZC
CY7C1518AV18-250BZI	CY7C1518AV18-250BZI
CY7C1518AV18-250BZXI	CY7C1518AV18-250BZXI
CY7C1520AV18-200BZC	CY7C1520AV18-200BZC
CY7C1520AV18-200BZXI	CY7C1520AV18-200BZXI
CY7C1520AV18-250BZXC	CY7C1520AV18-250BZXC
CY7C1520AV18-200BZCT	CY7C1520AV18-200BZCT

PDF Datasheet Preview
CY7C1518AV18 CY7C1520AV18 72-Mbit DDR-II SRAM Two-Word Burst Architecture 72-Mbit DDR-II SRAM Two-Word Burst Architecture • 72-Mbit density 4 M x 18, 2 M x 36 • 300-MHz clock for high bandwidth • Two-word burst for reducing address bus frequency • Double data rate DDR interfaces data transferred at 600 MHz at 300 MHz • Two input clocks K and K for precise DDR timing SRAM uses rising edges only • Two input clocks for output data C and C to minimize clock skew and flight time mismatches • Echo clocks CQ and CQ simplify data capture in high-speed systems • Synchronous internally self-timed writes • DDR-II operates with cycle read latency when delay lock loop DLL is enabled • Operates as a DDR-I device with one cycle read latency in DLL off mode • 1.8-V core power supply with HSTL inputs and outputs • Variable drive HSTL output buffers • Expanded HSTL output voltage • Available in 165-Ball FBGA package 15 x 17 x mm • Offered in both Pb-free and non Pb-free packages • JTAG compatible test access port • DLL for accurate data placement Configurations CY7C1518AV18 4 M x 18 CY7C1520AV18 2 M x 36 Functional Description The CY7C1518AV18, and CY7C1520AV18 are V synchronous pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C and C are not provided. On CY7C1518AV18 and CY7C1520AV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words in the case of CY7C1518AV18 and two 36-bit words in the case of CY7C1520AV18 sequentially into or out of the device. Asynchronous inputs include an output impedance matching the input ZQ . Synchronous data outputs Q, sharing the same physical pins as the data inputs D are tightly matched to the two output echo clocks CQ / CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. Output data clocks C / C enable maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Selection Guide Maximum operating frequency Maximum operating current 300 MHz 300 940 1080 278 MHz 278 860 985 250 MHz 250 800 900 200 MHz 200 700 735 167 MHz 167 650 Unit MHz mA • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C1518AV18 CY7C1520AV18 Logic Block Diagram CY7C1518AV18 Burst Logic A 21:0 22 21 A 21:1 Address Register K DOFF CLK Gen. VREF R/W BWS[1:0] Control Logic Write Reg Write Reg 2 M x 18 Array 2 M x 18 Array Power-up Sequence 18 DLL Constraints 18 Maximum Ratings 19 Operating Range 19 Electrical Characteristics 19 DC Electrical Characteristics 19 AC Electrical Characteristics 20 Capacitance 21 Thermal Resistance 21 Switching Characteristics 22 Switching Waveforms 24 Ordering Information 25 Ordering Code Definitions 25 Package Diagram 26 Acronyms 26 Document History Page 27 Sales, Solutions, and Legal Information 28 Worldwide Sales and Design Support 28 Products 28 PSoC Solutions 28 Page 3 of 28 [+] Feedback CY7C1518AV18 CY7C1520AV18 Pin Configuration The following table shows the pin configuration for parts, CY7C1518AV18 and CY7C1520AV18.[1] 165-Ball FBGA 15 x 17 x mm Pinout CY7C1518AV18 4 M x 18 BWS1 K NC/144M LD A NC/288M K BWS0 DQ10 DQ11 VDDQ VDDQ DQ12 VDDQ VDDQ DQ13 VDDQ VDDQ DOFF VREF VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQ14 VDDQ VDDQ DQ15 VDDQ VDDQ DQ16 DQ17 10 A NC DQ7 NC VREF DQ4 NC DQ1 NC TMS 11 CQ DQ8 NC DQ6 DQ5 NC ZQ NC DQ3 DQ2 NC DQ0 TDI CY7C1520AV18 2 M x 36 CQ NC/144M A Ordering Information Table 1 lists the CY7C1518AV18 and CY7C1520AV18 key package features and ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at Table Key Features and Ordering Information Speed MHz Ordering Code CY7C1518AV18-250BZC CY7C1520AV18-250BZC CY7C1520AV18-250BZXC CY7C1518AV18-250BZI CY7C1518AV18-250BZXI CY7C1520AV18-200BZC CY7C1520AV18-200BZI CY7C1520AV18-200BZXI CY7C1518AV18-167BZC Package Diagram Package Type 51-85195 165-Ball FBGA 15 x 17 x mm 165-Ball FBGA 15 x 17 x mm 165-Ball FBGA 15 x 17 x mm Pb-free 165-Ball FBGA 15 x 17 x mm 165-Ball FBGA 15 x 17 x mm Pb-free 51-85195 165-Ball FBGA 15 x 17 x mm 165-Ball FBGA 15 x 17 x mm 165-Ball FBGA 15 x 17 x mm Pb-free 51-85195 165-Ball FBGA 15 x 17 x mm Operating Range Commercial Industrial Commercial Industrial Commercial Ordering Code Definitions CY 7 C 15XX A V18 - XXX BZ X, C, I Package Type BZ = FBGA, X = Pb-free, C = Commercial, I = Industrial Maximum operating frequency Voltage V Errata fix PCN084656 72-Mbit DDR-II SRAM two-word burst architecture Technology CMOS Marketing Code 7 = SRAM Company ID CY = Cypress Page 25 of 28 [+] Feedback CY7C1518AV18 CY7C1520AV18 Package Diagram Figure 165-Ball FBGA 15 x 17 x mm PIN 1 CORNER TOP VIEW 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R SEATING PLANE C BOTTOM VIEW M C A B 165X 11 10 9 8 7 6 5 4 3 2 1 PIN 1 CORNER A B C D E F G H J K L M N P R B 0.15 4X NOTES SOLDER PAD TYPE NON SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.65g JEDEC REFERENCE MO-216 / ISSUE E PACKAGE CODE BB0AD MAX. Acronyms Acronym BWS CMOS DDR DLL FBGA HSTL I/O SRAM TCK TDI TDO TMS Description byte write select complementary metal oxide semiconductor double data rate delay lock loop fine pitch ball gird array high speed transceiver logic input/output static random access memory test clock test data in test data out test mode select 51-85195 *B Page 26 of 28 [+] Feedback CY7C1518AV18 CY7C1520AV18 Document History Page Document Title CY7C1518AV18/CY7C1520AV18, 72-Mbit DDR-II SRAM Two-Word Burst Architecture Document Number 001-06982 Orig. of Change Submission Date Description of Change 433241 See ECN New Datasheet Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information Updated package outline diagram. 2957481 06/21/2010 Included “CY7C1520AV18-200BZI” in the Ordering Information table Added Acronyms and Ordering Code Definitions Page 27 of 28 [+] Feedback CY7C1518AV18 CY7C1520AV18 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 28 of 28 [+] Feedback

PDF Datasheet Preview

CY7C1518AV18 CY7C1520AV18
72-Mbit DDR-II SRAM Two-Word Burst Architecture
72-Mbit DDR-II SRAM Two-Word Burst Architecture
• 72-Mbit density 4 M x 18, 2 M x 36
• 300-MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate DDR interfaces
data transferred at 600 MHz at 300 MHz
• Two input clocks K and K for precise DDR timing

SRAM uses rising edges only
• Two input clocks for output data C and C to minimize clock
skew and flight time mismatches
• Echo clocks CQ and CQ simplify data capture in high-speed
systems
• Synchronous internally self-timed writes
• DDR-II operates with cycle read latency when delay lock
loop DLL is enabled
• Operates as a DDR-I device with one cycle read latency in DLL
off mode
• 1.8-V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage
• Available in 165-Ball FBGA package 15 x 17 x mm
• Offered in both Pb-free and non Pb-free packages
• JTAG compatible test access port
• DLL for accurate data placement

Configurations

CY7C1518AV18 4 M x 18

CY7C1520AV18 2 M x 36

Functional Description

The CY7C1518AV18, and CY7C1520AV18 are V synchronous pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C and C are not provided. On CY7C1518AV18 and CY7C1520AV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words in the case of CY7C1518AV18 and two 36-bit words in the case of CY7C1520AV18 sequentially into or out of the device.

Asynchronous inputs include an output impedance matching the input ZQ . Synchronous data outputs Q, sharing the same physical pins as the data inputs D are tightly matched to the two output echo clocks CQ / CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. Output data clocks C / C enable maximum system clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Selection Guide

Maximum operating frequency

Maximum operating current
300 MHz 300 940 1080
278 MHz 278 860 985
250 MHz 250 800 900
200 MHz 200 700 735
167 MHz 167 650

Unit MHz mA
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C1518AV18 CY7C1520AV18

Logic Block Diagram CY7C1518AV18

Burst

Logic

A 21:0 22 21 A 21:1

Address Register

K DOFF

CLK Gen.

VREF R/W BWS[1:0]

Control Logic

Write Reg

Write Reg
2 M x 18 Array 2 M x 18 Array
Power-up Sequence 18 DLL Constraints 18 Maximum Ratings 19 Operating Range 19 Electrical Characteristics 19 DC Electrical Characteristics 19 AC Electrical Characteristics 20 Capacitance 21 Thermal Resistance 21 Switching Characteristics 22 Switching Waveforms 24 Ordering Information 25 Ordering Code Definitions 25 Package Diagram 26 Acronyms 26 Document History Page 27 Sales, Solutions, and Legal Information 28 Worldwide Sales and Design Support 28 Products 28 PSoC Solutions 28

Page 3 of 28 [+] Feedback

CY7C1518AV18 CY7C1520AV18

Pin Configuration

The following table shows the pin configuration for parts, CY7C1518AV18 and CY7C1520AV18.[1]
165-Ball FBGA 15 x 17 x mm Pinout

CY7C1518AV18 4 M x 18

BWS1

K NC/144M LD

A NC/288M K

BWS0

DQ10

DQ11

VDDQ

VDDQ

DQ12

VDDQ

VDDQ

DQ13

VDDQ

VDDQ

DOFF

VREF

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DQ14

VDDQ

VDDQ

DQ15

VDDQ

VDDQ

DQ16

DQ17
10 A NC DQ7 NC VREF DQ4 NC DQ1 NC TMS
11 CQ DQ8 NC DQ6 DQ5 NC ZQ NC DQ3 DQ2 NC DQ0 TDI

CY7C1520AV18 2 M x 36

CQ NC/144M A
Ordering Information
Table 1 lists the CY7C1518AV18 and CY7C1520AV18 key package features and ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at
Table Key Features and Ordering Information

Speed MHz
Ordering Code CY7C1518AV18-250BZC CY7C1520AV18-250BZC CY7C1520AV18-250BZXC CY7C1518AV18-250BZI CY7C1518AV18-250BZXI CY7C1520AV18-200BZC CY7C1520AV18-200BZI CY7C1520AV18-200BZXI CY7C1518AV18-167BZC

Package Diagram

Package Type
51-85195 165-Ball FBGA 15 x 17 x mm
165-Ball FBGA 15 x 17 x mm
165-Ball FBGA 15 x 17 x mm Pb-free
165-Ball FBGA 15 x 17 x mm
165-Ball FBGA 15 x 17 x mm Pb-free
51-85195 165-Ball FBGA 15 x 17 x mm
165-Ball FBGA 15 x 17 x mm
165-Ball FBGA 15 x 17 x mm Pb-free
51-85195 165-Ball FBGA 15 x 17 x mm

Operating Range

Commercial

Industrial

Commercial Industrial

Commercial
Ordering Code Definitions

CY 7 C
15XX

A V18 - XXX BZ X, C, I

Package Type BZ = FBGA, X = Pb-free, C = Commercial, I = Industrial

Maximum operating frequency

Voltage V

Errata fix PCN084656 72-Mbit DDR-II SRAM two-word burst architecture

Technology CMOS Marketing Code 7 = SRAM

Company ID CY = Cypress

Page 25 of 28 [+] Feedback

CY7C1518AV18 CY7C1520AV18

Package Diagram

Figure 165-Ball FBGA 15 x 17 x mm

PIN 1 CORNER

TOP VIEW
1 2 3 4 5 6 7 8 9 10 11

A B C D E F G H J K L M N P R

SEATING PLANE C

BOTTOM VIEW

M C A B
165X
11 10 9 8 7 6 5 4 3 2 1

PIN 1 CORNER

A B C D E F G H J K L M N P R

B 0.15 4X

NOTES SOLDER PAD TYPE NON SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.65g JEDEC REFERENCE MO-216 / ISSUE E PACKAGE CODE BB0AD

MAX.

Acronyms

Acronym BWS CMOS DDR DLL FBGA HSTL I/O SRAM TCK TDI TDO TMS

Description byte write select complementary metal oxide semiconductor double data rate delay lock loop fine pitch ball gird array high speed transceiver logic input/output static random access memory test clock test data in test data out test mode select
51-85195 *B

Page 26 of 28 [+] Feedback

CY7C1518AV18 CY7C1520AV18

Document History Page

Document Title CY7C1518AV18/CY7C1520AV18, 72-Mbit DDR-II SRAM Two-Word Burst Architecture Document Number 001-06982

Orig. of Change

Submission Date

Description of Change
433241

See ECN New Datasheet
Modified Ordering Information table by including parts that are available and
modified the disclaimer for the Ordering information Updated package outline diagram.
2957481
06/21/2010 Included “CY7C1520AV18-200BZI” in the Ordering Information table Added Acronyms and Ordering Code Definitions

Page 27 of 28 [+] Feedback

CY7C1518AV18 CY7C1520AV18

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

All products and company names mentioned in this document may be the trademarks of their respective holders.

Page 28 of 28
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1520AV18-250BZC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1520AV18-250BZC 508062