CPDVR105V0USP-HF
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CPDVR105V0USP-HF (pdf) |
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Low Capacitance ESD Protection Array CPDVR105V0USP-HF RoHS Device Halogen Free - IEC61000-4-2 Level 4 ESD Protection. - IEC61000-4-4 Level 4 FET protection. - Protects four high speed I/O lines - Low clamping voltage - Working Voltage 5V - Low leakage current Mechanical data - Case SLP2510P8 small outline plastic package - Terminals Matte tin plated, solderable per MIL-STD-202,method 208 - Mounting Compound Flammability Rating UL 94V-0 - High temperature soldering guaranteed: 260°C/10 second - Weight grams approx. . Circuit Diagram 12 3 45 SLP2510P8 0.02 0.50 BSC Dimensions in inches and millimeter 10 9 8 7 6 Electrical Characteristics TA=25 unless otherwise noted Parameter ESD capability Clamping voltage Peak pulse power Junction temperature range Storage temperature range Conditions I/O Pins to GND Note 1 IT = 1mA,I/O Pin to GND VRWM = 5V, I/O Pin to GND VR =0V, f =1MHz between I/Os VR =0V, f =1MHz between I/Os GND IEC 61000-4-2 Air IEC 61000-4-2 Contact IPP = 1A,I/O Pin to GND 8/20µs Tp=8/20µs waveform VRWM V BR IR CJ VESD VC PPP TJ TSTG -55 -55 Typ Max Unit ±15 kV QW-JP041 Comchip Technology CO., LTD. Low Capacitance ESD Protection Array Comchip SMD Diode Specialist RATING AND CHARACTERISTIC CURVES CPDVR105V0USP-HF Fig.1- Non-Repetitive Peak Pulse Power vs. Pulse Time Fig.2- Clamping Voltage vs. Peak Pulse Current Camping Voltage, V Peak Pulse Power, PPP KW Power Dissipation, mW Pulse Duration, us |
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