CS5378-ISZR

CS5378-ISZR Datasheet

CS5378

Part	Datasheet
CS5378-ISZR	CS5378-ISZR (pdf)

PDF Datasheet Preview
CS5378 Low-power Single-channel Decimation Filter Single-channel Digital Decimation Filter Multiple On-chip FIR and IIR Coefficient Sets Programmable Coefficients for Custom Filters Synchronous Operation Integrated PLL for Clock Generation MHz, MHz, or MHz Input Standard Clock or Manchester Input Selectable Output Word Rate 4000, 2000, 1000, 500, 333, 250 SPS 200, 125, 100, 50, 40, 25, 20, 10, 5, 1 SPS Digital Gain and Offset Corrections Test DAC Bit-stream Generator Digital Sine Wave Output Time Break Controller, General-purpose I/O Microcontroller or EEPROM Configuration Small-footprint, 28-pin SSOP Package Low Power Consumption 16 mW at 500 SPS OWR Flexible Power Supplies I/O Interface and PLL V or V Digital Logic Core V, V or V The CS5378 is a multi-function digital filter utilizing a lowpower signal processing architecture to achieve efficient filtering for a delta-sigma-type modulator. By combining the CS537 8 with a CS33 01A/02A di fferential a mplifier and a CS5373A modulator + test DAC, a synchronous high-resolution, self- testing, sin gle-channel m easurement system can be designed quickly and easily. Digital filter coefficients for the CS5378 FIR and IIR filters are included on-chip for a sim ple setup, or they can be programmed for custom ap plications. Selectable digital filter decimation r atios p roduce ou tput wor d r ates fro m 4000 SPS to 1 SPS, resulting in measurement bandwidths ra nging fro m 16 00 Hz down to 400 mHz whe n using the on-chip coefficient sets. The CS5378 includes integrated peripherals to simplify system d esign a low- jitter PL L for standard clo ck or Manchester inpu ts, offset and gain co rrections, a test DAC bit stream generator, a tim e break controller, and eight general-purpose I/O pins. ORDERING INFORMATION See page SS:EECS SCK MOSI MISO DRDY VDDPAD VDDPLL VDDCORE Serial Interface Decimation and Filtering Engine Modulator Data Interface PLL, Clock Generation Reset, Synchronization Time Break Controller Test Bit Stream Controller GPIO General Purpose I/O CLK MCLK RESET SYNC MSYNC TIMEB TBSDATA GPIO7:BOOT GPIO6:PLL2 GPIO5:PLL1 GPIO4:PLL0 GPIO3 GPIO2 GPIO1 GPIO0 MDATA MFLAG GNDPAD GNDPLL GNDCORE Copyright Cirrus Logic, Inc. 2010 All Rights Reserved 2&7 ‘10 DS639F3 CS5378 TABLE OF CONTENTS General Description 6 Digital Filter Features Integrated Peripheral Features System Level Features Configuration Interface. Characteristics and Specifications 12 Specified Operating Conditions Absolute Maximum Ratings Thermal Characteristics Digital Characteristics Power Consumption. Switching Characteristics System Design with CS5378. 18 Power Supplies Reset Control PLL and Clock Generation Synchronization System Configuration. Digital Filter Operation Data Collection. Integrated peripherals Power Supplies 20 Pin Descriptions Bypass Capacitors Power Consumption. Reset Control 21 Pin Descriptions Reset Self-Tests. Boot Configurations PLL and Clock Generation 22 Pin Descriptions PLL Mode Select Synchronous Clocking Master Clock Jitter and Skew. Synchronization. 24 Pin Description MSYNC Generation Digital Filter Synchronization Modulator Synchronization Test Bit Stream Synchronization Configuration By EEPROM. 25 Pin Descriptions EEPROM Hardware Interface EEPROM Organization EEPROM Configuration Commands Example EEPROM Configuration Configuration By Microcontroller 30 DS639F3 CS5378 Pin Descriptions Microcontroller Hardware Interface Microcontroller Serial Transactions Microcontroller Configuration Commands Example Microcontroller Configuration Modulator Interface 36 Pin Descriptions Modulator Clock Generation Modulator Synchronization. Modulator Data Input Modulator Flag Input Digital Filter Initialization 38 Ordering Information 86 Environmental, Manufacturing, & Handling Information 86 LIST OF FIGURES Figure CS5378 Block Diagram. 6 Figure Digital Filtering Stages 7 Figure FIR and IIR Coefficient Set Selection Word 10 Figure MOSI Write Timing in SPI Slave Mode 14 Figure MISO Read Timing in SPI Slave Mode. 14 Figure Serial Data Read Timing. 15 Figure SYNC, MCLK, MSYNC, MDATA Interface Timing. 16 Figure TBS Output Data Timing. 17 Figure Single-Channel System Block Diagram 18 Figure Power Supply Block Diagram 20 Figure Reset Control Block Diagram 21 Figure Clock Generation Block Diagram 22 Figure Synchronization Block Diagram 24 Figure EEPROM Configuration Block Diagram 25 Figure EEPROM Serial Read Transactions 26 Figure 8 Kbyte EEPROM Memory Organization 27 Figure Serial Interface Block Diagram 30 Figure Microcontroller Serial Transactions. 31 Figure SPI Registers 32 Figure Modulator Data Interface 36 Figure Digital Filter Stages. 38 Figure FIR and IIR Coefficient Set Selection Word 39 Figure SINC Filter Block Diagram 40 Figure SINC Filter Stages 41 Figure FIR Filter Block Diagram. 44 Figure FIR Filter Stages 46 Figure FIR1 Coefficients 49 Figure FIR2 Linear Phase Coefficients 50 DS639F3 CS5378 Figure FIR2 Minimum Phase Coefficients 51 Figure IIR Filter Block Diagram 52 Figure IIR Filter Stages 54 Figure Gain and Offset Correction 56 Figure Serial Data Interface Block Diagram. 58 Figure 32-bit Serial Data Format 58 Figure SD Port Transaction 59 Figure Test Bit Stream Generator Block Diagram 60 Figure Time Break Block Diagram 63 Figure GPIO Block Diagram. 64 Figure SPI Control Register SPICTRL 67 Figure SPI Command Register SPICMD 68 Figure SPI Data Register SPIDAT1 69 Figure SPI Data Register SPIDAT2 70 Figure Hardware Configuration Register CONFIG. 72 Figure GPIO Configuration Register GPCFG 73 Figure Filter Configuration Register FILTCFG 74 Figure Gain Correction Register GAIN. 75 Figure Offset Correction Register OFFSET 76 Figure Time Break Counter Register TIMEBRK 77 Figure Test Bit Stream Configuration Register TBSCFG. 78 Figure Test Bit Stream Gain Register TBSGAIN 79 Figure User Defined System Register SYSTEM1 80 Figure Hardware Version ID Register VERSION 81 Figure Self Test Result Register SELFTEST 82 Figure CS5378 Pin Assignments 83 LIST OF TABLES Table Microcontroller and EEPROM Configuration Commands 9 Table TBS Configurations Using On-Chip Data. 10 Table SPI and Digital Filter Registers 11 Table PLL and BOOT Mode Reset Configurations 11 Table PLL Mode Selections 22 Table Maximum EEPROM Configuration. 27 Table EEPROM Boot Configuration Commands 28 Table Example EEPROM File 29 Table Microcontroller Boot Configuration Commands 33 Table Example Microcontroller Configuration 35 Table SINC Filter Configurations 41 Table SINC1 and SINC2 Filter Coefficients 42 Table SINC3 Filter Coefficients 43 Table FIR Filter Characteristics 46 Table SINC + FIR Group Delay 47 Table Minimum Phase Group Delay 48 Table IIR Filter Characteristics. 54 Table IIR Filter Coefficients 55 Table TBS Configurations Using On-chip Data 61 DS639F3 CS5378 SS:EECS SCK MOSI MISO DRDY VDDPAD VDDPLL VDDCORE Serial Interface Decimation and Filtering Engine Modulator Data Interface PLL, Clock Generation Reset, Synchronization Time Break Controller Test Bit Stream Controller GPIO General Purpose I/O CLK MCLK RESET SYNC MSYNC TIMEB TBSDATA GPIO7:BOOT GPIO6:PLL2 GPIO5:PLL1 GPIO4:PLL0 GPIO3 GPIO2 GPIO1 GPIO0 MDATA MFLAG GNDPAD GNDPLL GNDCORE Figure CS5378 Block Diagram GENERAL DESCRIPTION The CS5378 is a single channel digital filter with integrated system peripherals. Figure 1 illustrates a simplified block diagram of the CS5378. Digital Filter Features • Single channel decimation filter for CS5373A modulator. • Synchronous operation for simultaneous sam- pling in multi-sensor systems. - Internal synchronization of digital filter phase to an external SYNC signal. • Output word rates, including low bandwidth rates. - Standard output rates 4000, 2000, 1000, 500, 333, 250 SPS. - Low bandwidth rates 200, 125, 100, 50, 40, 25, 20, 10, 5, 1 SPS. • Flexible digital filter configuration. See Figure 2 - Cascaded SINC, FIR, and IIR filters with selectable output stage. - Linear and minimum phase FIR low-pass filter coefficients included. - 3 Hz Butterworth IIR high-pass filter coefficients included. - FIR and IIR coefficients programmable to create a custom filter response. • Digital gain correction to normalize sensor gain. • Digital offset correction and calibration. 23.ORDERING INFORMATION Model CS5378-ISZ Lead Free Temperature -40 to +85 °C CS5378 Package 28-pin SSOP 24.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS5378-ISZ Lead Free Peak Reflow Temp 260 °C MSL Rating* 3 Max Floor Life 7 Days * MSL Moisture Sensitivity Level as specified by IPC/JEDEC J-STD-020. DS639F3 CS5378 25.REVISION HISTORY Date FEB 2004 OCT 2005 SEP 2008 OCT 2010 Removed lead-containing device ordering information. DS639F3 CS5378 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries "Cirrus" believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind express or implied . Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE "CRITICAL APPLICATIONS" . CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRU S PRODUCT THAT IS USED IN SUCH A MANNER. I F THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OT HER AGENTS FROM ANY AND AL L LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. DS639F3

PDF Datasheet Preview

CS5378

Low-power Single-channel Decimation Filter

Single-channel Digital Decimation Filter

Multiple On-chip FIR and IIR Coefficient Sets Programmable Coefficients for Custom Filters Synchronous Operation

Integrated PLL for Clock Generation

MHz, MHz, or MHz Input Standard Clock or Manchester Input

Selectable Output Word Rate
4000, 2000, 1000, 500, 333, 250 SPS 200, 125, 100, 50, 40, 25, 20, 10, 5, 1 SPS

Digital Gain and Offset Corrections Test DAC Bit-stream Generator

Digital Sine Wave Output

Time Break Controller, General-purpose I/O Microcontroller or EEPROM Configuration Small-footprint, 28-pin SSOP Package Low Power Consumption
16 mW at 500 SPS OWR

Flexible Power Supplies

I/O Interface and PLL V or V Digital Logic Core V, V or V

The CS5378 is a multi-function digital filter utilizing a lowpower signal processing architecture to achieve efficient filtering for a delta-sigma-type modulator. By combining the CS537 8 with a CS33 01A/02A di fferential a mplifier and a CS5373A modulator + test DAC, a synchronous high-resolution, self- testing, sin gle-channel m easurement system can be designed quickly and easily.

Digital filter coefficients for the CS5378 FIR and IIR filters are included on-chip for a sim ple setup, or they can be programmed for custom ap plications. Selectable digital filter decimation r atios p roduce ou tput wor d r ates fro m 4000 SPS to 1 SPS, resulting in measurement bandwidths ra nging fro m 16 00 Hz down to 400 mHz whe n using the on-chip coefficient sets.

The CS5378 includes integrated peripherals to simplify system d esign a low- jitter PL L for standard clo ck or Manchester inpu ts, offset and gain co rrections, a test DAC bit stream generator, a tim e break controller, and eight general-purpose I/O pins.
ORDERING INFORMATION See page

SS:EECS SCK MOSI MISO DRDY VDDPAD VDDPLL VDDCORE

Serial Interface

Decimation and Filtering Engine

Modulator Data Interface

PLL, Clock Generation Reset, Synchronization

Time Break Controller

Test Bit Stream Controller

GPIO General Purpose I/O

CLK MCLK RESET SYNC MSYNC

TIMEB

TBSDATA

GPIO7:BOOT GPIO6:PLL2 GPIO5:PLL1 GPIO4:PLL0 GPIO3 GPIO2 GPIO1 GPIO0

MDATA MFLAG GNDPAD GNDPLL GNDCORE

Copyright Cirrus Logic, Inc. 2010 All Rights Reserved
2&7 ‘10 DS639F3

CS5378

TABLE OF CONTENTS

General Description 6

Digital Filter Features Integrated Peripheral Features System Level Features Configuration Interface.

Characteristics and Specifications 12

Specified Operating Conditions Absolute Maximum Ratings Thermal Characteristics Digital Characteristics Power Consumption. Switching Characteristics

System Design with CS5378. 18

Power Supplies Reset Control PLL and Clock Generation Synchronization System Configuration. Digital Filter Operation Data Collection. Integrated peripherals

Power Supplies 20

Pin Descriptions Bypass Capacitors Power Consumption.

Reset Control 21

Pin Descriptions Reset Self-Tests. Boot Configurations

PLL and Clock Generation 22

Pin Descriptions PLL Mode Select Synchronous Clocking Master Clock Jitter and Skew.

Synchronization. 24

Pin Description MSYNC Generation Digital Filter Synchronization Modulator Synchronization Test Bit Stream Synchronization

Configuration By EEPROM. 25

Pin Descriptions EEPROM Hardware Interface EEPROM Organization EEPROM Configuration Commands Example EEPROM Configuration

Configuration By Microcontroller 30

DS639F3

CS5378

Pin Descriptions Microcontroller Hardware Interface Microcontroller Serial Transactions Microcontroller Configuration Commands Example Microcontroller Configuration

Modulator Interface 36

Pin Descriptions Modulator Clock Generation Modulator Synchronization. Modulator Data Input Modulator Flag Input

Digital Filter Initialization 38
Ordering Information 86

Environmental, Manufacturing, & Handling Information 86

LIST OF FIGURES

Figure CS5378 Block Diagram. 6 Figure Digital Filtering Stages 7 Figure FIR and IIR Coefficient Set Selection Word 10 Figure MOSI Write Timing in SPI Slave Mode 14 Figure MISO Read Timing in SPI Slave Mode. 14 Figure Serial Data Read Timing. 15 Figure SYNC, MCLK, MSYNC, MDATA Interface Timing. 16 Figure TBS Output Data Timing. 17 Figure Single-Channel System Block Diagram 18 Figure Power Supply Block Diagram 20 Figure Reset Control Block Diagram 21 Figure Clock Generation Block Diagram 22 Figure Synchronization Block Diagram 24 Figure EEPROM Configuration Block Diagram 25 Figure EEPROM Serial Read Transactions 26 Figure 8 Kbyte EEPROM Memory Organization 27 Figure Serial Interface Block Diagram 30 Figure Microcontroller Serial Transactions. 31 Figure SPI Registers 32 Figure Modulator Data Interface 36 Figure Digital Filter Stages. 38 Figure FIR and IIR Coefficient Set Selection Word 39 Figure SINC Filter Block Diagram 40 Figure SINC Filter Stages 41 Figure FIR Filter Block Diagram. 44 Figure FIR Filter Stages 46 Figure FIR1 Coefficients 49 Figure FIR2 Linear Phase Coefficients 50

DS639F3

CS5378

Figure FIR2 Minimum Phase Coefficients 51 Figure IIR Filter Block Diagram 52 Figure IIR Filter Stages 54 Figure Gain and Offset Correction 56 Figure Serial Data Interface Block Diagram. 58 Figure 32-bit Serial Data Format 58 Figure SD Port Transaction 59 Figure Test Bit Stream Generator Block Diagram 60 Figure Time Break Block Diagram 63 Figure GPIO Block Diagram. 64 Figure SPI Control Register SPICTRL 67 Figure SPI Command Register SPICMD 68 Figure SPI Data Register SPIDAT1 69 Figure SPI Data Register SPIDAT2 70 Figure Hardware Configuration Register CONFIG. 72 Figure GPIO Configuration Register GPCFG 73 Figure Filter Configuration Register FILTCFG 74 Figure Gain Correction Register GAIN. 75 Figure Offset Correction Register OFFSET 76 Figure Time Break Counter Register TIMEBRK 77 Figure Test Bit Stream Configuration Register TBSCFG. 78 Figure Test Bit Stream Gain Register TBSGAIN 79 Figure User Defined System Register SYSTEM1 80 Figure Hardware Version ID Register VERSION 81 Figure Self Test Result Register SELFTEST 82 Figure CS5378 Pin Assignments 83

LIST OF TABLES

Table Microcontroller and EEPROM Configuration Commands 9 Table TBS Configurations Using On-Chip Data. 10 Table SPI and Digital Filter Registers 11 Table PLL and BOOT Mode Reset Configurations 11 Table PLL Mode Selections 22 Table Maximum EEPROM Configuration. 27 Table EEPROM Boot Configuration Commands 28 Table Example EEPROM File 29 Table Microcontroller Boot Configuration Commands 33 Table Example Microcontroller Configuration 35 Table SINC Filter Configurations 41 Table SINC1 and SINC2 Filter Coefficients 42 Table SINC3 Filter Coefficients 43 Table FIR Filter Characteristics 46 Table SINC + FIR Group Delay 47 Table Minimum Phase Group Delay 48 Table IIR Filter Characteristics. 54 Table IIR Filter Coefficients 55 Table TBS Configurations Using On-chip Data 61

DS639F3

CS5378

SS:EECS SCK MOSI MISO DRDY VDDPAD VDDPLL VDDCORE

Serial Interface

Decimation and Filtering Engine

Modulator Data Interface

PLL, Clock Generation Reset, Synchronization

Time Break Controller

Test Bit Stream Controller

GPIO General Purpose I/O

CLK MCLK RESET SYNC MSYNC

TIMEB

TBSDATA

GPIO7:BOOT GPIO6:PLL2 GPIO5:PLL1 GPIO4:PLL0 GPIO3 GPIO2 GPIO1 GPIO0

MDATA MFLAG GNDPAD GNDPLL GNDCORE

Figure CS5378 Block Diagram

GENERAL DESCRIPTION The CS5378 is a single channel digital filter with integrated system peripherals. Figure 1 illustrates a simplified block diagram of the CS5378.

Digital Filter Features
• Single channel decimation filter for CS5373A
modulator.
• Synchronous operation for simultaneous sam-
pling in multi-sensor systems.
- Internal synchronization of digital filter phase to an external SYNC signal.
• Output word rates, including low bandwidth rates.
- Standard output rates 4000, 2000, 1000, 500, 333, 250 SPS.
- Low bandwidth rates 200, 125, 100, 50,
40, 25, 20, 10, 5, 1 SPS.
• Flexible digital filter configuration. See Figure 2
- Cascaded SINC, FIR, and IIR filters with selectable output stage.
- Linear and minimum phase FIR low-pass filter coefficients included.
- 3 Hz Butterworth IIR high-pass filter coefficients included.
- FIR and IIR coefficients programmable to create a custom filter response.
• Digital gain correction to normalize sensor gain.
• Digital offset correction and calibration.
23.ORDERING INFORMATION

Model CS5378-ISZ Lead Free

Temperature -40 to +85 °C

CS5378

Package 28-pin SSOP
24.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION

Model Number CS5378-ISZ Lead Free

Peak Reflow Temp 260 °C

MSL Rating* 3

Max Floor Life 7 Days
* MSL Moisture Sensitivity Level as specified by IPC/JEDEC J-STD-020.

DS639F3

CS5378
25.REVISION HISTORY

Date FEB 2004 OCT 2005 SEP 2008 OCT 2010
Removed lead-containing device ordering information.

DS639F3

CS5378

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to

IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries "Cirrus" believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind express or implied . Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE "CRITICAL APPLICATIONS" . CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRU S PRODUCT THAT IS USED IN SUCH A MANNER. I F THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OT HER AGENTS FROM ANY AND AL L LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc.

DS639F3

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CS5378-ISZR Datasheet file may be downloaded here without warranties.

Datasheet ID: CS5378-ISZR 523196