CS4353-DZZ

CS4353-DZZ Datasheet

CS4353

Part	Datasheet
CS4353-DZZ	CS4353-DZZ (pdf)

Related Parts	Information
CS4353-CZZR	CS4353-CZZR
CS4353-DNZ	CS4353-DNZ
CS4353-DZZR	CS4353-DZZR
CS4353-CZZ	CS4353-CZZ

PDF Datasheet Preview
CS4353 V Stereo Audio DAC with 2 VRMS Line Output Multi-bit Delta-Sigma Modulator 106 dB A-wt Dynamic Range -93 dB THD+N Single-ended Ground Centered Analog Architecture No DC-blocking Capacitors Required Integrated Step-up/Inverting Charge Pump Filtered Line-level Outputs Selectable 1 or 2 VRMS Full-scale Output Low Clock-jitter Sensitivity Low-latency Digital Filtering Supports Sample Rates up to 192 kHz 24-bit Resolution V Charge Pump and Core Logic, V Analog, and to V Interface Power Supplies Low Power Consumption 24-pin QFN, Lead-free Assembly The CS4353 is a complete stereo digital-to-analog system including digital interpolation, fifth-order multi-bit delta-sigma digital-to-analog conversion, digital de-emphasis, analog filtering, and on-chip 2 VRMS line-level driver from a V supply. The advantages of this architecture include ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature, high tolerance to clock jitter, and a minimal set of external components. The CS4353 is available in a 24-pin QFN package in Commercial -40°C to +85°C grade. The CDB4353 Customer Demonstration Board is also available for device evaluation and implementation suggestions. Please see “Ordering Information” on page 25 for complete details. These features are ideal for cost-sensitive, 2-channel audio systems including video game consoles, DVD players and recorders, A/V receivers, set-top boxes, digital TVs, mini-component systems, and mixing consoles. Interface Supply VL V to V Digital Core Logic and Charge Pump Supply VCP Analog Supply VA V Reset Hardware Control Serial Audio Input Level Shifter Hardware Control PCM Serial Audio Port Auto Speed Mode Detect Power-On Reset Interpolation Filters Multibit Modulator Step-Up Inverting +VA_H -VA_H Ground-Centered, 2 Vrms Line Level Outputs Left Channel Pseudo Diff. Input Right Channel Copyright Cirrus Logic, Inc. 2009 All Rights Reserved JUN '09 DS803F1 CS4353 TABLE OF CONTENTS PIN DESCRIPTIONS 4 CHARACTERISTICS AND SPECIFICATIONS 6 RECOMMENDED OPERATING CONDITIONS 6 ABSOLUTE MAXIMUM RATINGS 6 DAC ANALOG CHARACTERISTICS 7 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE 8 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE 9 DIGITAL INTERFACE CHARACTERISTICS 10 INTERNAL POWER-ON RESET THRESHOLD VOLTAGES 10 DC ELECTRICAL CHARACTERISTICS 11 TYPICAL CONNECTION DIAGRAM 12 APPLICATIONS 13 Ground-centered Outputs 13 Full-scale Output Amplitude Control 13 Pseudo-differential Outputs 13 Power-up Sequences 19 DS803F1 CS4353 LIST OF FIGURES Figure 1.Serial Input Timing 9 Figure 2.Power-on Reset Threshold Sequence 10 Figure 3.Typical Connection Diagram 12 Figure 4.Stereo Pseudo-differential Output 13 Figure up to 24-bit Data 15 Figure 6.Left-justified up to 24-bit Data 15 Figure 7.De-emphasis Curve, Fs = kHz 16 Figure 8.Internal Power-on Reset Circuit 16 Figure 9.Initialization and Power-down Sequence Diagram 18 Figure 10.Single-speed Stopband Rejection 21 Figure 11.Single-speed Transition Band 21 Figure 12.Single-speed Transition Band detail 21 Figure 13.Single-speed Passband Ripple 21 Figure 14.Double-speed Stopband Rejection 21 Figure 15.Double-speed Transition Band 21 Figure 16.Double-speed Transition Band detail 22 Figure 17.Double-speed Passband Ripple 22 Figure 18.Quad-speed Stopband Rejection 22 Figure 19.Quad-speed Transition Band 22 Figure 20.Quad-speed Transition Band detail 22 Figure 21.Quad-speed Passband Ripple 22 LIST OF TABLES Table Digital I/O Pin Characteristics 11 Table CS4353 Operational Mode Auto-Detect 14 Table Single-speed Mode Standard Frequencies 14 Table Double-speed Mode Standard Frequencies 14 Table Quad-speed Mode Standard Frequencies 14 Table Digital Interface Format 15 DS803F1 PIN DESCRIPTIONS CS4353 SDIN LRCK DEM 1_2VRMS RESET 24 23 22 21 20 19 SCLK 1 MCLK 2 VL 3 DGND 4 FLYP- 5 VCP 6 Thermal Pad Top-Down Through Package View 24-Pin QFN Package 18 VBIAS 17 VA 16 AGND 15 AOUTA 14 AOUT_REF 13 AOUTB 7 8 9 10 11 12 FLYP+ VFILT+ FLYN+ CPGND FLYNVFILT- Pin Name Pin # Pin Description SCLK 1 Serial Clock Input - Serial clock for the serial audio interface. MCLK 2 Master Clock Input - Clock source for the delta-sigma modulator and digital filters. 3 Serial Audio Interface Power Input - Positive power for the serial audio interface DGND 4 Digital Ground Input - Ground reference for the digital section. FLYP+ FLYP- 7 Step-up Charge Pump Cap Positive/Negative Nodes Output - Positive and Negative nodes for the 5 step-up charge pump’s flying capacitor. Charge Pump and Digital Core Logic Power Input - Positive power supply for the step-up and inverting charge pumps as well as the digital core logic sections. VFILT+ Step-up Charge Pump Filter Connection Output - Power supply from the step-up charge pump that provides the positive rail for the output amplifiers FLYN+ FLYN- 9 Inverting Charge Pump Cap Positive/Negative Nodes Output - Positive and Negative nodes for the 11 inverting charge pump’s flying capacitor. CPGND 10 Charge Pump Ground Input - Ground reference for the Charge Pump section. VFILT- Inverting Charge Pump Filter Connection Output - Power supply from the inverting charge pump that provides the negative rail for the output amplifiers. AOUTB AOUTA 13 Analog Outputs Output - The full-scale analog line output level is specified in the Analog Characteris15 tics table. ORDERING INFORMATION Product CS4353 CDB4353 Package V Stereo Audio DAC with 2 VRMS Line Output 24-pin QFN CS4353 Evaluation Board Pb-Free YES - Grade Commercial Temp Range -40° to +85° C Container Rail Tape & Reel - Order # CS4353-CNZ CS4353-CNZR CDB4353 Release PP1 PP2 F1 Changes Updated interchannel isolation specification in the DAC Analog Characteristics specification table. Updated minimum Quad-Speed Mode SCLK period in the Switching Specifications - Serial Audio Interface table. Updated power supply current and power dissipation specifications in the DC Electrical Characteristics table. Updated the FLYN+ to FLYN- DC voltage in the DC Electrical Characteristics table. Added “SDIN = 0” to the test conditions in the DC Electrical Characteristics table. Updated Section on page Updated output impedance specification in the DAC Analog Characteristics specification table. Removed Automotive Grade. Added Note 2 and reference to Note 4 in the Dynamic Performance section of the DAC Analog Characteristics table. Changed “additional” to “external” in Note 6 and 8 on page Updated full scale output specification in the DAC Analog Characteristics table. Updated Von2 and Voff specifications in the Internal Power-on Reset Threshold Voltages table. Added HPF data to Combined Interpolation & On-Chip Analog Filter Response table. Added Section Internal High-Pass Filter. DS803F1 CS4353 Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries “Cirrus” believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind express or implied . Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE “CRITICAL APPLICATIONS” . CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. DS803F1

PDF Datasheet Preview

CS4353

V Stereo Audio DAC with 2 VRMS Line Output

Multi-bit Delta-Sigma Modulator 106 dB A-wt Dynamic Range -93 dB THD+N

Single-ended Ground Centered Analog Architecture No DC-blocking Capacitors Required Integrated Step-up/Inverting Charge Pump Filtered Line-level Outputs Selectable 1 or 2 VRMS Full-scale Output

Low Clock-jitter Sensitivity Low-latency Digital Filtering Supports Sample Rates up to 192 kHz 24-bit Resolution V Charge Pump and Core Logic, V

Analog, and to V Interface Power Supplies Low Power Consumption 24-pin QFN, Lead-free Assembly

The CS4353 is a complete stereo digital-to-analog system including digital interpolation, fifth-order multi-bit delta-sigma digital-to-analog conversion, digital de-emphasis, analog filtering, and on-chip 2 VRMS line-level driver from a V supply.

The advantages of this architecture include ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature, high tolerance to clock jitter, and a minimal set of external components.
The CS4353 is available in a 24-pin QFN package in Commercial -40°C to +85°C grade. The CDB4353 Customer Demonstration Board is also available for device evaluation and implementation suggestions. Please see “Ordering Information” on page 25 for complete details.

These features are ideal for cost-sensitive, 2-channel audio systems including video game consoles, DVD players and recorders, A/V receivers, set-top boxes, digital TVs, mini-component systems, and mixing consoles.

Interface Supply VL V to V

Digital Core Logic and Charge Pump Supply VCP

Analog Supply VA V

Reset

Hardware Control

Serial Audio Input

Level Shifter

Hardware Control

PCM Serial Audio Port

Auto Speed Mode Detect

Power-On Reset

Interpolation Filters

Multibit Modulator

Step-Up Inverting
+VA_H -VA_H

Ground-Centered, 2 Vrms Line Level Outputs

Left Channel

Pseudo Diff. Input

Right Channel

Copyright Cirrus Logic, Inc. 2009 All Rights Reserved

JUN '09 DS803F1

CS4353

TABLE OF CONTENTS

PIN DESCRIPTIONS 4 CHARACTERISTICS AND SPECIFICATIONS 6

RECOMMENDED OPERATING CONDITIONS 6 ABSOLUTE MAXIMUM RATINGS 6 DAC ANALOG CHARACTERISTICS 7 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE 8 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE 9 DIGITAL INTERFACE CHARACTERISTICS 10 INTERNAL POWER-ON RESET THRESHOLD VOLTAGES 10 DC ELECTRICAL CHARACTERISTICS 11 TYPICAL CONNECTION DIAGRAM 12 APPLICATIONS 13

Ground-centered Outputs 13 Full-scale Output Amplitude Control 13 Pseudo-differential Outputs 13 Power-up Sequences 19
DS803F1

CS4353

LIST OF FIGURES

Figure 1.Serial Input Timing 9 Figure 2.Power-on Reset Threshold Sequence 10 Figure 3.Typical Connection Diagram 12 Figure 4.Stereo Pseudo-differential Output 13 Figure up to 24-bit Data 15 Figure 6.Left-justified up to 24-bit Data 15 Figure 7.De-emphasis Curve, Fs = kHz 16 Figure 8.Internal Power-on Reset Circuit 16 Figure 9.Initialization and Power-down Sequence Diagram 18 Figure 10.Single-speed Stopband Rejection 21 Figure 11.Single-speed Transition Band 21 Figure 12.Single-speed Transition Band detail 21 Figure 13.Single-speed Passband Ripple 21 Figure 14.Double-speed Stopband Rejection 21 Figure 15.Double-speed Transition Band 21 Figure 16.Double-speed Transition Band detail 22 Figure 17.Double-speed Passband Ripple 22 Figure 18.Quad-speed Stopband Rejection 22 Figure 19.Quad-speed Transition Band 22 Figure 20.Quad-speed Transition Band detail 22 Figure 21.Quad-speed Passband Ripple 22

LIST OF TABLES

Table Digital I/O Pin Characteristics 11 Table CS4353 Operational Mode Auto-Detect 14 Table Single-speed Mode Standard Frequencies 14 Table Double-speed Mode Standard Frequencies 14 Table Quad-speed Mode Standard Frequencies 14 Table Digital Interface Format 15

DS803F1

PIN DESCRIPTIONS

CS4353

SDIN LRCK DEM 1_2VRMS RESET
24 23 22 21 20 19

SCLK 1 MCLK 2

VL 3 DGND 4 FLYP- 5

VCP 6

Thermal Pad

Top-Down Through Package View 24-Pin QFN Package
18 VBIAS 17 VA 16 AGND 15 AOUTA 14 AOUT_REF 13 AOUTB
7 8 9 10 11 12

FLYP+ VFILT+ FLYN+ CPGND FLYNVFILT-

Pin Name Pin #

Pin Description

SCLK
1 Serial Clock Input - Serial clock for the serial audio interface.

MCLK
2 Master Clock Input - Clock source for the delta-sigma modulator and digital filters.
3 Serial Audio Interface Power Input - Positive power for the serial audio interface

DGND
4 Digital Ground Input - Ground reference for the digital section.

FLYP+ FLYP-
7 Step-up Charge Pump Cap Positive/Negative Nodes Output - Positive and Negative nodes for the 5 step-up charge pump’s flying capacitor.

Charge Pump and Digital Core Logic Power Input - Positive power supply for the step-up and inverting charge pumps as well as the digital core logic sections.

VFILT+

Step-up Charge Pump Filter Connection Output - Power supply from the step-up charge pump that provides the positive rail for the output amplifiers

FLYN+ FLYN-
9 Inverting Charge Pump Cap Positive/Negative Nodes Output - Positive and Negative nodes for the 11 inverting charge pump’s flying capacitor.

CPGND
10 Charge Pump Ground Input - Ground reference for the Charge Pump section.

VFILT-

Inverting Charge Pump Filter Connection Output - Power supply from the inverting charge pump that provides the negative rail for the output amplifiers.

AOUTB AOUTA
13 Analog Outputs Output - The full-scale analog line output level is specified in the Analog Characteris15 tics table.
ORDERING INFORMATION

Product CS4353 CDB4353

Package

V Stereo Audio DAC with 2 VRMS Line Output 24-pin QFN

CS4353 Evaluation Board

Pb-Free YES -

Grade Commercial

Temp Range -40° to +85° C

Container Rail

Tape & Reel -

Order # CS4353-CNZ CS4353-CNZR

CDB4353

Release PP1 PP2 F1

Changes Updated interchannel isolation specification in the DAC Analog Characteristics specification table. Updated minimum Quad-Speed Mode SCLK period in the Switching Specifications - Serial Audio Interface table. Updated power supply current and power dissipation specifications in the DC Electrical Characteristics table. Updated the FLYN+ to FLYN- DC voltage in the DC Electrical Characteristics table. Added “SDIN = 0” to the test conditions in the DC Electrical Characteristics table. Updated Section on page Updated output impedance specification in the DAC Analog Characteristics specification table. Removed Automotive Grade. Added Note 2 and reference to Note 4 in the Dynamic Performance section of the DAC Analog Characteristics
table. Changed “additional” to “external” in Note 6 and 8 on page Updated full scale output specification in the DAC Analog Characteristics table. Updated Von2 and Voff specifications in the Internal Power-on Reset Threshold Voltages table. Added HPF data to Combined Interpolation & On-Chip Analog Filter Response table. Added Section Internal High-Pass Filter.

DS803F1

CS4353

Contacting Cirrus Logic Support

For all product questions and inquiries, contact a Cirrus Logic Sales Representative.

To find one nearest you, go to

IMPORTANT NOTICE

Cirrus Logic, Inc. and its subsidiaries “Cirrus” believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind express or implied . Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE “CRITICAL APPLICATIONS” . CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.

DS803F1

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CS4353-DZZ Datasheet file may be downloaded here without warranties.

Datasheet ID: CS4353-DZZ 523181