CS42324-CQZ

CS42324-CQZ Datasheet

CS42324

Part	Datasheet
CS42324-CQZ	CS42324-CQZ (pdf)

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CS42324 10-In, 6-Out, 2 Vrms Audio CODEC D/A Features Dual 24-bit Stereo DACs Multi-bit Delta-Sigma Modulator 100 dB Dynamic Range A-Wtd -90 dB THD+N Integrated Line Driver 2 Vrms Output Single-Ended Outputs Up to 96 kHz Sampling Rates Stereo 7:1 Output Multiplexer Volume Control with Soft Ramp dB Step Size Zero Crossing Click-Free Transitions Selectable Serial Audio Interface Formats Left- or Right-Justified, Up to 24-bit Up to 24-bit Selectable 50/15 us De-Emphasis Internal Analog Mute Control Output for External Muting Technology A/D Features Multi-bit Delta-Sigma Modulator 24-bit Conversion Up to 96 kHz Sampling Rates 95 dB Dynamic Range A-Wtd -88 dB THD+N Stereo 5:1 Input Multiplexer Digital Volume Control with Soft Ramp dB Step Size Selectable Serial Audio Interface Formats Left-Justified High-Pass Filter or DC Offset Calibration See System Features, General Description, and Ordering information on page V to V 9 V to12 V Serial Audio Inputs SPI & I2C Control Data Interrupt ADC Overflow Reset Serial Audio Output Level Translator Level Translator Level Translator PCM Serial Interface Volume Control/Mixer Multibit Modulator Volume Control/Mixer Multibit Modulator Stereo DAC Stereo DAC Register Configuration Internal Voltage Reference 7:1 MUX Mute 7:1 MUX Mute 7:1 MUX Mute Mute Control Volume Control/High Pass Filter Low-Latency Decimation Filter Multibit Oversampling Stereo ADC 5:1 MUX Stereo Output 1 Stereo Output 2 Stereo Output 3 Mute 1 Mute 2 Mute 3 Stereo Input 1 Stereo Input 2 Stereo Input 3 Stereo Input 4 Stereo Input 5 PCM Serial Interface Advance Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc. 2008 All Rights Reserved JANUARY '08 DS721A6 System Features The CS42324 is available in a 48-pin LQFP package in Commercial -40°C to +85°C and Automotive -40°C to +105°C grades. The CDB42324 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please refer to “Ordering information” on page 71 for complete details. DS721A6 CS42324 TABLE OF CONTENTS PIN DESCRIPTIONS 8 Software Mode 8 Hardware Mode 10 Digital I/O Pin Characteristics 12 CHARACTERISTICS AND SPECIFICATIONS 13 RECOMMENDED OPERATING CONDITIONS 13 ABSOLUTE MAXIMUM RATINGS 13 DAC ANALOG CHARACTERISTICS - COMMERCIAL -CQZ 14 DAC ANALOG CHARACTERISTICS - AUTOMOTIVE -DQZ 15 DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE 16 ADC ANALOG CHARACTERISTICS - COMMERCIAL -CQZ 17 ADC ANALOG CHARACTERISTICS - AUTOMOTIVE -DQZ 18 ADC DIGITAL FILTER CHARACTERISTICS 19 ANALOG PASS-THRU CHARACTERISTICS 20 DC ELECTRICAL CHARACTERISTICS 21 DIGITAL INTERFACE CHARACTERISTICS 21 SWITCHING CHARACTERISTICS - SERIAL AUDIO 22 SWITCHING CHARACTERISTICS - SERIAL AUDIO CONT. 23 SWITCHING CHARACTERISTICS - SOFTWARE MODE - FORMAT 24 SWITCHING CHARACTERISTICS - SOFTWARE MODE - SPI FORMAT 25 TYPICAL CONNECTION DIAGRAMS 26 APPLICATIONS 28 System Clocking 28 Master Clock 28 Synchronous / Asynchronous Mode 29 Serial Port Operation 29 Master Mode 30 Slave Mode 30 ADC, DAC1, and DAC2 clock selection 31 High-Impedance Digital Output 31 Digital Interface Formats 32 Synchronization of Multiple Devices 32 Analog-to-Digital Data Path 33 ADC Analog Input Multiplexer 33 ADC Description 33 High-Pass Filter and DC Offset Calibration 34 Digital Attenuation Control 34 Digital-to-Analog Data Path 34 Digital Volume Control 34 Mono Channel Mixer 34 De-Emphasis Filter 35 Internal Digital Loopback 35 DAC Description 35 Analog Output Multiplexer 36 Output Transient Control 36 Mute Control 37 Initialization 37 Determining Hardware or Software Mode 37 Hardware Mode Start-Up 37 Software Mode Start-Up 38 Initialization Flow Chart 39 Device Control 40 DS721A6 CS42324 DS721A6 CS42324 DS721A6 CS42324 LIST OF FIGURES Figure 1.Equivalent Analog Output Load 16 Figure 2.Maximum Analog Output Loading 16 Figure 3.Serial Input Timing 22 Figure 4.Serial Output Timing 23 Figure 5.Software Mode Timing - Format 24 Figure 6.Software Mode Timing - SPI Mode 25 Figure 7.Typical Connection Diagram - Software Mode 26 Figure 8.Typical Connection Diagram - Hardware Mode 27 Figure 9.Serial Port Topology 29 Figure 10.Master Mode Clock Generation 30 Figure 11.Converter Clocking 31 Figure 12.Tri-State Serial Port 31 Figure 13.Left-Justified up to 24-Bit Data 32 Figure up to 24-Bit Data 32 Figure 15.Right-Justified 16-Bit Data, Right-Justified 24-Bit Data 32 Figure 16.Analog Input Architecture 33 Figure 17.De-Emphasis Curve 35 Figure 18.Analog Output Architecture 36 Figure 19.Initialization Flow Chart 39 Figure 20.Software Mode Timing, Write 41 Figure 21.Software Mode Timing, Read 41 Figure 22.Software Mode Timing, SPI Mode 43 Figure 23.Single-Speed Mode Stopband Rejection 65 Figure 24.Single-Speed Mode Transition Band 65 Figure 25.Single-Speed Mode Transition Band Detail 65 Figure 26.Single-Speed Mode Passband Ripple 65 Figure 27.Double-Speed Mode Stopband Rejection 65 Figure 28.Double-Speed Mode Transition Band 65 Figure 29.Double-Speed Mode Transition Band Detail 66 Figure 30.Double-Speed Mode Passband Ripple 66 Figure 31.Single-Speed Stopband Rejection 67 Figure 32.Single-Speed Transition Band 67 Figure 33.Single-Speed Transition Band detail 67 Figure 34.Single-Speed Passband Ripple 67 Figure 35.Double-Speed Stopband Rejection 67 Figure 36.Double-Speed Transition Band 67 Figure 37.Double-Speed Transition Band detail 68 Figure 38.Double-Speed Passband Ripple 68 Figure 39.Quad-Speed Stopband Rejection 68 Figure 40.Quad-Speed Transition Band 68 Figure 41.Quad-Speed Transition Band detail 68 Figure 42.Quad-Speed Passband Ripple 68 LIST OF TABLES Table I/O Power Rails 12 Table Speed Modes 28 Table Single-Speed Mode Common Clock Frequencies 28 Table Double-Speed Mode Common Clock Frequencies 28 Table M1 and M0 Mode Pins in Hardware Mode 29 Table Slave Mode SCLK/LRCK Ratios 30 Table MCLKx to LRCKx Ratios 30 Table Hardware Mode Interface Format Control 32 DS721A6 CS42324 Table Hardware Mode Feature Summary 40 Table Freeze-able Bits 48 DS721A6 PIN DESCRIPTIONS Software Mode CS42324 MCLK1 LRCK1 SCLK1 SDOUT VL GND VD SCLK2 LRCK2 MCLK2 SDIN1 SDIN2 SDA/CDOUT SCL/CCLK AD0/CS AD1/CDIN INT FILT+ VCMADC GND VA VBIAS MUTEC1 MUTEC2 48 47 46 45 44 43 42 41 40 39 38 37 CS42324 13 14 15 16 17 18 19 20 21 22 23 24 OVFL RST AIN1A AIN1B AIN2A AIN2B AIN3A AIN3B AIN4A AIN4B AIN5A AIN5B MUTEC3 VCMBUF VCMDAC VA_H GNDH VA_H AOUT1A AOUT1B AOUT2A AOUT2B AOUT3A AOUT3B Pin Name SDA/CDOUT SCL/CCLK AD0/CS AD1/CDIN INT FILT+ VCMADC GND VA VBIAS MUTEC1 Pin Description Format SDA Input/Output - Acts as an input/output data pin. An external pull-up resistor is 1 required for control port operation. SPI Format CDOUT Output - Acts as an output only data pin. Format, SCL Input Serial clock for the serial control port. An external pull-up resistor is 2 required for control port operation. SPI Format, CCLK Input Serial clock for the serial control port. Format, AD0 Input - Forms the device address input AD[0]. SPI Format, CS Input - Acts as the active low chip select input. Format, AD1 Input - Forms the device address input AD[1]. SPI Format, CDIN Input - Becomes the input data pin. 5 Interrupt Output - Indicates an interrupt condition has occurred. 6 FILT+ Output - Full-scale reference voltage for ADC. ADC Common-Mode Voltage Output - Filter connections for the ADC internal quiescent reference voltage. 8 Analog Ground Input - Analog ground reference. 9 Analog Power Input - Positive power for the internal analog section. 10 Bias Voltage Output - Positive reference voltage for the internal DAC. Mute Control 1 Output - Active-low mute output can drive external circuitry to eliminate the 11 clicks and pops associated with any single-rail output. This pin will become a high-impedance out- put during power-down mode or when an invalid MCLK to LRCK ratio is detected. DS721A6 CS42324 12.ORDERING INFORMATION Product Package 2-In, 4-Out Audio CS42324 CODEC with 2Vrms LQFP Analog I/O 2-In, 4-Out Audio CS42324 CODEC with 2Vrms LQFP Analog I/O CDB42324 Evaluation Board Pb-Free Grade Temp Range Yes Commercial -40°C to +85° C Yes Automotive -40°C to +105° C Container Tray Tray - CS42324 Order # CS42324-CQZ CS42324-DQZ CDB42324 13.REVISION HISTORY Release A5 A6 Changes Changed Title Corrected SCL/CCLK pin description Pin 2 in the Pin Description table on page Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to IMPORTANT NOTICE "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries "Cirrus" believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind express or implied . Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE “CRITICAL APPLICATIONS” . CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. is a registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc. DS721A6

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CS42324
10-In, 6-Out, 2 Vrms Audio CODEC

D/A Features

Dual 24-bit Stereo DACs Multi-bit Delta-Sigma Modulator 100 dB Dynamic Range A-Wtd -90 dB THD+N Integrated Line Driver
2 Vrms Output Single-Ended Outputs Up to 96 kHz Sampling Rates Stereo 7:1 Output Multiplexer Volume Control with Soft Ramp dB Step Size Zero Crossing Click-Free Transitions

Selectable Serial Audio Interface Formats Left- or Right-Justified, Up to 24-bit Up to 24-bit

Selectable 50/15 us De-Emphasis Internal Analog Mute Control Output for External Muting Technology

A/D Features

Multi-bit Delta-Sigma Modulator 24-bit Conversion Up to 96 kHz Sampling Rates 95 dB Dynamic Range A-Wtd -88 dB THD+N Stereo 5:1 Input Multiplexer Digital Volume Control with Soft Ramp
dB Step Size

Selectable Serial Audio Interface Formats Left-Justified

High-Pass Filter or DC Offset Calibration
See System Features, General Description, and Ordering information on page

V to V
9 V to12 V

Serial Audio Inputs

SPI & I2C Control Data

Interrupt ADC Overflow

Reset

Serial Audio Output

Level Translator

Level Translator

Level Translator PCM Serial Interface

Volume Control/Mixer

Multibit Modulator

Volume Control/Mixer

Multibit Modulator

Stereo DAC Stereo DAC

Register Configuration

Internal Voltage Reference
7:1 MUX

Mute
7:1 MUX

Mute
7:1 MUX

Mute

Mute Control

Volume Control/High Pass Filter

Low-Latency Decimation

Filter

Multibit Oversampling Stereo ADC
5:1 MUX

Stereo Output 1

Stereo Output 2

Stereo Output 3

Mute 1 Mute 2 Mute 3

Stereo Input 1 Stereo Input 2 Stereo Input 3 Stereo Input 4 Stereo Input 5

PCM Serial Interface

Advance Product Information

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

Copyright Cirrus Logic, Inc. 2008 All Rights Reserved

JANUARY '08 DS721A6

System Features
The CS42324 is available in a 48-pin LQFP package in Commercial -40°C to +85°C and Automotive -40°C to +105°C grades. The CDB42324 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please refer to “Ordering information” on page 71 for complete details.

DS721A6

CS42324

TABLE OF CONTENTS

PIN DESCRIPTIONS 8 Software Mode 8 Hardware Mode 10 Digital I/O Pin Characteristics 12

CHARACTERISTICS AND SPECIFICATIONS 13 RECOMMENDED OPERATING CONDITIONS 13 ABSOLUTE MAXIMUM RATINGS 13 DAC ANALOG CHARACTERISTICS - COMMERCIAL -CQZ 14 DAC ANALOG CHARACTERISTICS - AUTOMOTIVE -DQZ 15 DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE 16 ADC ANALOG CHARACTERISTICS - COMMERCIAL -CQZ 17 ADC ANALOG CHARACTERISTICS - AUTOMOTIVE -DQZ 18 ADC DIGITAL FILTER CHARACTERISTICS 19 ANALOG PASS-THRU CHARACTERISTICS 20 DC ELECTRICAL CHARACTERISTICS 21 DIGITAL INTERFACE CHARACTERISTICS 21 SWITCHING CHARACTERISTICS - SERIAL AUDIO 22 SWITCHING CHARACTERISTICS - SERIAL AUDIO CONT. 23 SWITCHING CHARACTERISTICS - SOFTWARE MODE - FORMAT 24 SWITCHING CHARACTERISTICS - SOFTWARE MODE - SPI FORMAT 25

TYPICAL CONNECTION DIAGRAMS 26 APPLICATIONS 28

System Clocking 28 Master Clock 28 Synchronous / Asynchronous Mode 29

Serial Port Operation 29 Master Mode 30 Slave Mode 30 ADC, DAC1, and DAC2 clock selection 31 High-Impedance Digital Output 31 Digital Interface Formats 32 Synchronization of Multiple Devices 32

Analog-to-Digital Data Path 33 ADC Analog Input Multiplexer 33 ADC Description 33 High-Pass Filter and DC Offset Calibration 34 Digital Attenuation Control 34

Digital-to-Analog Data Path 34 Digital Volume Control 34 Mono Channel Mixer 34 De-Emphasis Filter 35 Internal Digital Loopback 35 DAC Description 35 Analog Output Multiplexer 36 Output Transient Control 36 Mute Control 37

Initialization 37 Determining Hardware or Software Mode 37 Hardware Mode Start-Up 37 Software Mode Start-Up 38 Initialization Flow Chart 39

Device Control 40

DS721A6

CS42324

DS721A6

CS42324
DS721A6

CS42324

LIST OF FIGURES

Figure 1.Equivalent Analog Output Load 16 Figure 2.Maximum Analog Output Loading 16 Figure 3.Serial Input Timing 22 Figure 4.Serial Output Timing 23 Figure 5.Software Mode Timing - Format 24 Figure 6.Software Mode Timing - SPI Mode 25 Figure 7.Typical Connection Diagram - Software Mode 26 Figure 8.Typical Connection Diagram - Hardware Mode 27 Figure 9.Serial Port Topology 29 Figure 10.Master Mode Clock Generation 30 Figure 11.Converter Clocking 31 Figure 12.Tri-State Serial Port 31 Figure 13.Left-Justified up to 24-Bit Data 32 Figure up to 24-Bit Data 32 Figure 15.Right-Justified 16-Bit Data, Right-Justified 24-Bit Data 32 Figure 16.Analog Input Architecture 33 Figure 17.De-Emphasis Curve 35 Figure 18.Analog Output Architecture 36 Figure 19.Initialization Flow Chart 39 Figure 20.Software Mode Timing, Write 41 Figure 21.Software Mode Timing, Read 41 Figure 22.Software Mode Timing, SPI Mode 43 Figure 23.Single-Speed Mode Stopband Rejection 65 Figure 24.Single-Speed Mode Transition Band 65 Figure 25.Single-Speed Mode Transition Band Detail 65 Figure 26.Single-Speed Mode Passband Ripple 65 Figure 27.Double-Speed Mode Stopband Rejection 65 Figure 28.Double-Speed Mode Transition Band 65 Figure 29.Double-Speed Mode Transition Band Detail 66 Figure 30.Double-Speed Mode Passband Ripple 66 Figure 31.Single-Speed Stopband Rejection 67 Figure 32.Single-Speed Transition Band 67 Figure 33.Single-Speed Transition Band detail 67 Figure 34.Single-Speed Passband Ripple 67 Figure 35.Double-Speed Stopband Rejection 67 Figure 36.Double-Speed Transition Band 67 Figure 37.Double-Speed Transition Band detail 68 Figure 38.Double-Speed Passband Ripple 68 Figure 39.Quad-Speed Stopband Rejection 68 Figure 40.Quad-Speed Transition Band 68 Figure 41.Quad-Speed Transition Band detail 68 Figure 42.Quad-Speed Passband Ripple 68

LIST OF TABLES

Table I/O Power Rails 12 Table Speed Modes 28 Table Single-Speed Mode Common Clock Frequencies 28 Table Double-Speed Mode Common Clock Frequencies 28 Table M1 and M0 Mode Pins in Hardware Mode 29 Table Slave Mode SCLK/LRCK Ratios 30 Table MCLKx to LRCKx Ratios 30 Table Hardware Mode Interface Format Control 32

DS721A6

CS42324

Table Hardware Mode Feature Summary 40 Table Freeze-able Bits 48

DS721A6

PIN DESCRIPTIONS

Software Mode

CS42324

MCLK1 LRCK1 SCLK1 SDOUT VL GND VD SCLK2 LRCK2 MCLK2 SDIN1 SDIN2

SDA/CDOUT SCL/CCLK AD0/CS AD1/CDIN INT FILT+ VCMADC GND VA VBIAS MUTEC1 MUTEC2
48 47 46 45 44 43 42 41 40 39 38 37

CS42324
13 14 15 16 17 18 19 20 21 22 23 24

OVFL RST AIN1A AIN1B AIN2A AIN2B AIN3A AIN3B AIN4A AIN4B AIN5A AIN5B

MUTEC3 VCMBUF VCMDAC

VA_H GNDH VA_H AOUT1A AOUT1B AOUT2A AOUT2B AOUT3A AOUT3B

Pin Name SDA/CDOUT

SCL/CCLK

AD0/CS AD1/CDIN INT FILT+ VCMADC GND VA VBIAS MUTEC1

Pin Description

Format SDA Input/Output - Acts as an input/output data pin. An external pull-up resistor is 1 required for control port operation.

SPI Format CDOUT Output - Acts as an output only data pin.

Format, SCL Input Serial clock for the serial control port. An external pull-up resistor is 2 required for control port operation.

SPI Format, CCLK Input Serial clock for the serial control port.

Format, AD0 Input - Forms the device address input AD[0]. SPI Format, CS Input - Acts as the active low chip select input.

Format, AD1 Input - Forms the device address input AD[1]. SPI Format, CDIN Input - Becomes the input data pin.
5 Interrupt Output - Indicates an interrupt condition has occurred.
6 FILT+ Output - Full-scale reference voltage for ADC.

ADC Common-Mode Voltage Output - Filter connections for the ADC internal quiescent reference voltage.
8 Analog Ground Input - Analog ground reference.
9 Analog Power Input - Positive power for the internal analog section.
10 Bias Voltage Output - Positive reference voltage for the internal DAC.

Mute Control 1 Output - Active-low mute output can drive external circuitry to eliminate the 11 clicks and pops associated with any single-rail output. This pin will become a high-impedance out-
put during power-down mode or when an invalid MCLK to LRCK ratio is detected.

DS721A6

CS42324
12.ORDERING INFORMATION

Product

Package
2-In, 4-Out Audio

CS42324 CODEC with 2Vrms LQFP

Analog I/O
2-In, 4-Out Audio

CS42324 CODEC with 2Vrms LQFP

Analog I/O

CDB42324

Evaluation Board

Pb-Free Grade

Temp Range

Yes Commercial -40°C to +85° C

Yes Automotive -40°C to +105° C

Container Tray

Tray -

CS42324

Order # CS42324-CQZ CS42324-DQZ

CDB42324
13.REVISION HISTORY

Release A5 A6

Changes Changed Title Corrected SCL/CCLK pin description Pin 2 in the Pin Description table on page

Contacting Cirrus Logic Support

For all product questions and inquiries, contact a Cirrus Logic Sales Representative.

To find one nearest you, go to

IMPORTANT NOTICE
"Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries "Cirrus" believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind express or implied . Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE “CRITICAL APPLICATIONS” . CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
is a registered trademark of Philips Semiconductor.

SPI is a trademark of Motorola, Inc.

DS721A6

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CS42324-CQZ Datasheet file may be downloaded here without warranties.

Datasheet ID: CS42324-CQZ 523160