DM96L02N

DM96L02N Datasheet

DM96L02 Dual Retriggerable Resettable Monostable Multivibrator

Part	Datasheet
DM96L02N	DM96L02N (pdf)

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DM96L02 Dual Retriggerable Resettable Monostable Multivibrator DM96L02 Dual Retriggerable Resettable Monostable Multivibrator The DM96L02 is a dual TTL monostable multivibrator with trigger mode selection, reset capability, rapid recovery, internally compensated reference levels and high speed capability. Output pulse duration and accuracy depend on external timing components, and are therefore under user control for each application. It is well suited for a broad variety of applications, including pulse delay generators, square wave generators, long delay timers, pulse absence detectors, frequency detectors, clock pulse generators and fixed-frequency dividers. Each input is provided with a clamp diode to limit undershoot and minimize ringing induced by fast fall times acting on system wiring impedances. s Retriggerable, 0% to 100% duty cycle s DC level triggering, insensitive to transition times s Leading or trailing-edge triggering s Complementary outputs with active pull-ups s Pulse width compensation for and s 50 ns to ∞ output pulse width range s Optional retrigger lock-out capability s Resettable, for interrupt operations Ordering Code: Order Number Package Number Package Description DM96L02N N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Logic Symbol Connection Diagram VCC = Pin 16 GND = Pin 8 Pin Descriptions Pin Names I0 I1 CD Q CX RX Trigger Input Active Falling Edge Trigger Input Active Rising Edge Direct Clear Input Active LOW Positive Pulse Output Complementary Pulse Output External Capacitor Connection External Resistor Connection 2000 Fairchild Semiconductor Corporation DS010203 DM96L02 Functional Block Diagram Operation Notes be accomplished by a positivegoing transition on pin 4 12 or a negative-going transition on pin 5 Triggering begins as a signal crosses the input VIL:VIH threshold region this activates an internal latch whose unbalanced cross-coupling causes it to assume a preferred state. As the latch output goes LOW it disables the gates leading to the Q output and, through an inverter, turns on the capacitor discharge transistor. The inverted signal is also fed back to the latch input to change its state and effectively end the triggering action thus the latch and its associated feedback perform the function of a differentiator. The emitters of the latch transistors return to ground through an enabling transistor which must be turned off between successive triggers in order for the latch to proceed through the proper sequence when triggering is desired. Pin 5 11 must be HIGH in order to trigger at pin 4 12 conversely, pin 4 12 must be LOW in order to trigger at pin 5 NON-RETRIGGERABLE can be inhibited logically, by connecting pin 6 10 back to pin 4 12 or by connecting pin 7 9 back to pin 5 Either hook-up has the effect of keeping the latchenabling transistor turned on during the delay period, which prevents the input latch from cycling as discussed above in the section on triggering. OUTPUT PULSE external resistor RX and an external capacitor CX are required, as shown in the functional block diagram. To minimize stray capacitance and noise pickup, RX and CX should be located as close as possible to the circuit. In applications which require remote trimming of the pulse width, as with a variable resistor, RX should consist of a fixed resistor in series with the variable resistor the fixed resistor should be located as close as possible to the circuit. The output pulse width tW is defined as follows, where RX is in CX is in pF and tW is in ns. tW = RXCX 1 + 3/RX for CX 103 pF 16 RX 220 for 0°C to +75°C 20 RX 100 for −55°C to +125°C CX may vary from 0 to any value. For pulse widths with CX less than 103 pF see Figure SETUP AND RELEASE setup times listed below are necessary to allow the latch-enabling transistor to turn off and the node voltages within the input latch to stabilize, thus insuring proper cycling of the latch when the next trigger occurs. The indicated release times equivalent to trigger duration allow time for the input latch to cycle and its signal to propagate. RESET LOW signal on CD, pin 3 13 , will terminate an output pulse, causing Q to go LOW and Q to go HIGH. As long as CD is held LOW, a delay period cannot be initiated nor will attempted triggering cause spikes at the outputs. A reset pulse duration, in the LOW state, of 25 ns is sufficient to insure resetting. If the reset input goes LOW at the same time that a trigger transition occurs, the reset will dominate and the outputs will not respond to the trigger. If the reset input goes HIGH coincident with a trigger transition, the circuit will respond to the trigger. Input to Pin 5 11 Pin 4 12 = L Pin 3 13 = H Input to Pin 4 12 Pins 5 11 and 3 13 = H DM96L02 96L02 Pulse Width vs. RX and CX Typical Characteristics tw vs. VCC FIGURE tw min vs. TA tw vs. TA INPUT PULSE f 25 kHz Amp 3.0V Width 100 ns tr = tf 10 ns FIGURE

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DM96L02 Dual Retriggerable Resettable Monostable Multivibrator

DM96L02 Dual Retriggerable Resettable Monostable Multivibrator

The DM96L02 is a dual TTL monostable multivibrator with trigger mode selection, reset capability, rapid recovery, internally compensated reference levels and high speed capability. Output pulse duration and accuracy depend on external timing components, and are therefore under user control for each application. It is well suited for a broad variety of applications, including pulse delay generators, square wave generators, long delay timers, pulse absence detectors, frequency detectors, clock pulse generators and fixed-frequency dividers. Each input is provided with a clamp diode to limit undershoot and minimize ringing induced by fast fall times acting on system wiring impedances.
s Retriggerable, 0% to 100% duty cycle s DC level triggering, insensitive to transition times s Leading or trailing-edge triggering s Complementary outputs with active pull-ups s Pulse width compensation for and s 50 ns to ∞ output pulse width range s Optional retrigger lock-out capability s Resettable, for interrupt operations
Ordering Code:

Order Number Package Number

Package Description

DM96L02N

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide

Logic Symbol

Connection Diagram

VCC = Pin 16

GND = Pin 8

Pin Descriptions

Pin Names

I0 I1 CD Q CX RX

Trigger Input Active Falling Edge Trigger Input Active Rising Edge Direct Clear Input Active LOW Positive Pulse Output Complementary Pulse Output External Capacitor Connection External Resistor Connection
2000 Fairchild Semiconductor Corporation DS010203

DM96L02

Functional Block Diagram

Operation Notes
be accomplished by a positivegoing transition on pin 4 12 or a negative-going transition on pin 5 Triggering begins as a signal crosses the input VIL:VIH threshold region this activates an internal latch whose unbalanced cross-coupling causes it to assume a preferred state. As the latch output goes LOW it disables the gates leading to the Q output and, through an inverter, turns on the capacitor discharge transistor. The inverted signal is also fed back to the latch input to change its state and effectively end the triggering action thus the latch and its associated feedback perform the function of a differentiator.

The emitters of the latch transistors return to ground through an enabling transistor which must be turned off between successive triggers in order for the latch to proceed through the proper sequence when triggering is desired. Pin 5 11 must be HIGH in order to trigger at pin 4 12 conversely, pin 4 12 must be LOW in order to trigger at pin 5

NON-RETRIGGERABLE can be inhibited logically, by connecting pin 6 10 back to pin 4 12 or by connecting pin 7 9 back to pin 5 Either hook-up has the effect of keeping the latchenabling transistor turned on during the delay period, which prevents the input latch from cycling as discussed above in the section on triggering.

OUTPUT PULSE external resistor RX and an external capacitor CX are required, as shown in the functional block diagram. To minimize stray capacitance and noise pickup, RX and CX should be located as close as possible to the circuit. In applications which require remote trimming of the pulse width, as with a variable resistor, RX should consist of a fixed resistor in series with the variable resistor the fixed resistor should be located as close as possible to the circuit. The output pulse width tW is defined as follows, where RX is in CX is in pF and tW is in ns.
tW = RXCX 1 + 3/RX for CX 103 pF
16 RX 220 for 0°C to +75°C
20 RX 100 for −55°C to +125°C

CX may vary from 0 to any value. For pulse widths with CX less than 103 pF see Figure

SETUP AND RELEASE setup times listed below are necessary to allow the latch-enabling transistor to turn off and the node voltages within the input latch to stabilize, thus insuring proper cycling of the latch when the next trigger occurs. The indicated release times equivalent to trigger duration allow time for the input latch to cycle and its signal to propagate.

RESET LOW signal on CD, pin 3 13 , will terminate an output pulse, causing Q to go LOW and Q to go HIGH. As long as CD is held LOW, a delay period cannot be initiated nor will attempted triggering cause spikes at the outputs. A reset pulse duration, in the LOW state, of 25 ns is sufficient to insure resetting. If the reset input goes LOW at the same time that a trigger transition occurs, the reset will dominate and the outputs will not respond to the trigger. If the reset input goes HIGH coincident with a trigger transition, the circuit will respond to the trigger.

Input to Pin 5 11

Pin 4 12 = L

Pin 3 13 = H

Input to Pin 4 12

Pins 5 11 and 3 13 = H

DM96L02
96L02 Pulse Width vs. RX and CX

Typical Characteristics
tw vs. VCC

FIGURE
tw min vs. TA tw vs. TA

INPUT PULSE f 25 kHz Amp 3.0V Width 100 ns tr = tf 10 ns

FIGURE

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Datasheet ID: DM96L02N 513854