VMMK-3803-TR2G

VMMK-3803-TR2G Datasheet

VMMK-3803 3 - 11 GHz UWB Low Noise Amplifier in SMT Package

Part	Datasheet
VMMK-3803-TR2G	VMMK-3803-TR2G (pdf)

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VMMK-3803 3 - 11 GHz UWB Low Noise Amplifier in SMT Package Data Sheet WLP0402, 1 mm x mm x mm Pin Connections Top View • 1 x mm surface mount package • Ultrathin mm • Wide frequency range • Self-Biasing 3 to 5 V • In and output match 50 ohm Specifications 6 GHz, Vdd = 3 V, Vpd = 3 V, Zin = Zout = 50 • Low noise figure dB typ. • Small signal gain 20 dB typ. • Output Power at 1dB compression = 7 dBm • GHz UWB LNA • and 5-6 GHz WLAN and WiMax • GHz PMP • & BWA systems • Radar and ECM systems • Generic IF amplifier Input Output/Vdd Input Output/Vdd Attention Observe precautions for handling electrostatic sensitive devices. ESD Machine Model = 60 V ESD Human Body Model = 200 V Refer to Avago Application Note A004R Electrostatic Discharge, Damage and Control. Note “O” = Device Code “Y” = Month Code Electrical Specifications Table Absolute Maximum Rating [1] Parameters/Condition Unit Absolute Max Supply Voltage RF Output Power Down Voltage Idd [2] Supply Current Pin, max [3] Pdiss Tch CW RF Input Power RF Input Total Power Dissipation Max Channel Temperature +150 Thermal Resistance °C/W Notes Operation of this device above any one of these parameters may cause permanent damage Bias is assumed DC quiescent conditions With the DC typical bias and RF applied to the device at board temperature Tb = 25° C Thermal resistance is measured from junction to board using IR method Table DC and RF Specifications [1] TA = 25° C, Zin = Zout = 50 Freq = 6 GHz, Vdd = 3 V, Vpd = 3 V unless otherwise specified Parameters/Condition Unit Minimum Idd [2] Supply Current Idd_Off [2] Leakage Current Vpd = 0 V Ga [2,3] Gain NF [2,3] Noise Figure Ordering Information Part Number VMMK-3803-BLKG VMMK-3803-TR1G Devices Per Container 100 5000 Container Antistatic Bag 7” Reel Outline Drawing PIN ONE INDICATOR MIN, MAX MIN, MAX GROUND PAD INPUT PAD Notes Solderable area of the device shown in yellow. Dimensions in mm. Tolerance ± 0.015mm OUTPUT PAD Suggested PCB Material and Land Pattern fy the device rial with one tal. Soldering ion than FR5 materials with e of the base vice circuitry aAs package to damaging RO4003 and al and should Part of Input Circuit Part of Output Circuit source leads of the unt. The recern is shown ned footprint t borders the en. re any plated ng and tests in and re 5 provides VMMK-3XXX ness RO4350 e also applies t frequencies 1XXX FETs at uctance may ay be placed bility. Consult ation. of the VMMK that the VIAs om under the of the VIAs is e VIAs should max 2pl see discussion dia PTH 4pl Solder Mask dia 4pl NFiogtueres:5. Recommended PCB layout for VMMK devices Rogers RO4350 As a general rule, if a VIA is within 100u of the edge of the soldermask but not under the device, then the VIA should be filled. Any VIA which is covered by the solder mask and is beyond 100u of the solder mask edge can be uncapped and unfilled as it is not at risk of wicking away solder from the device. If for any reason it is required to include a VIA or VIAs under a VMMK device, then the VIAs should be filled and capped. A capped VIA is a “plated over” filled VIA. If a filled but uncapped VIA is placed under the device, there will not be enough solderable surface area for device attach- ment. If an unfilled and uncapped VIA is placed directly under the ground pad, then the liquid solder will flow into the open VIA hole during the reflow process and deplete the solder volume to varying degrees from 9udnudeetro the ground pad. unfilled VIAs may Depletion of the solder volume lead to a weak solder joint, poor grounding of the device, and/or stresses compromising the structural integrity of the package. Recommended SMT Attachment

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VMMK-3803 3 - 11 GHz UWB Low Noise Amplifier in SMT Package

Data Sheet

WLP0402, 1 mm x mm x mm

Pin Connections Top View
• 1 x mm surface mount package
• Ultrathin mm
• Wide frequency range
• Self-Biasing 3 to 5 V
• In and output match 50 ohm

Specifications 6 GHz, Vdd = 3 V, Vpd = 3 V, Zin = Zout = 50
• Low noise figure dB typ.
• Small signal gain 20 dB typ.
• Output Power at 1dB compression = 7 dBm
• GHz UWB LNA
• and 5-6 GHz WLAN and WiMax
• GHz PMP
• & BWA systems
• Radar and ECM systems
• Generic IF amplifier

Input

Output/Vdd

Input

Output/Vdd

Attention Observe precautions for handling electrostatic sensitive devices. ESD Machine Model = 60 V ESD Human Body Model = 200 V Refer to Avago Application Note A004R Electrostatic Discharge, Damage and Control.

Note “O” = Device Code “Y” = Month Code

Electrical Specifications

Table Absolute Maximum Rating [1]

Parameters/Condition

Unit

Absolute Max

Supply Voltage RF Output

Power Down Voltage

Idd [2]

Supply Current

Pin, max [3] Pdiss Tch

CW RF Input Power RF Input Total Power Dissipation Max Channel Temperature
+150

Thermal Resistance
°C/W

Notes Operation of this device above any one of these parameters may cause permanent damage Bias is assumed DC quiescent conditions With the DC typical bias and RF applied to the device at board temperature Tb = 25° C Thermal resistance is measured from junction to board using IR method

Table DC and RF Specifications [1] TA = 25° C, Zin = Zout = 50 Freq = 6 GHz, Vdd = 3 V, Vpd = 3 V unless otherwise specified

Parameters/Condition

Unit

Minimum

Idd [2]

Supply Current

Idd_Off [2]

Leakage Current Vpd = 0 V

Ga [2,3]

Gain

NF [2,3]

Noise Figure
Ordering Information

Part Number VMMK-3803-BLKG VMMK-3803-TR1G

Devices Per Container 100
5000

Container Antistatic Bag 7” Reel

Outline Drawing

PIN ONE INDICATOR

MIN, MAX

MIN, MAX

GROUND PAD

INPUT PAD

Notes Solderable area of the device shown in yellow. Dimensions in mm. Tolerance ± 0.015mm

OUTPUT PAD

Suggested PCB Material and Land Pattern
fy the device rial with one tal. Soldering ion than FR5 materials with e of the base vice circuitry aAs package to damaging RO4003 and al and should

Part of Input Circuit

Part of Output Circuit
source leads of the unt. The recern is shown ned footprint t borders the en.
re any plated ng and tests in and re 5 provides

VMMK-3XXX ness RO4350 e also applies t frequencies 1XXX FETs at uctance may ay be placed bility. Consult ation.
of the VMMK that the VIAs om under the of the VIAs is e VIAs should
max 2pl see discussion
dia PTH 4pl Solder Mask
dia 4pl

NFiogtueres:5. Recommended PCB layout for VMMK devices Rogers RO4350

As a general rule, if a VIA is within 100u of the edge of the soldermask but not under the device, then the VIA should be filled. Any VIA which is covered by the solder mask and is beyond 100u of the solder mask edge can be uncapped and unfilled as it is not at risk of wicking away solder from the device.

If for any reason it is required to include a VIA or VIAs
under a VMMK device, then the VIAs should be filled and
capped. A capped VIA is a “plated over” filled VIA. If a filled
but uncapped VIA is placed under the device, there will
not be enough solderable surface area for device attach-
ment. If an unfilled and uncapped VIA is placed directly
under the ground pad, then the liquid solder will flow
into the open VIA hole during the reflow process and
deplete the solder volume to varying degrees from
9udnudeetro
the ground pad. unfilled VIAs may

Depletion of the solder volume lead to a weak solder joint, poor
grounding of the device, and/or stresses compromising
the structural integrity of the package.

Recommended SMT Attachment

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Datasheet ID: VMMK-3803-TR2G 520535