W40S01-04H

W40S01-04H Datasheet


1W40S01-04

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W40S01-04H W40S01-04H W40S01-04H (pdf)
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1W40S01-04

W40S01-04
• Eighteen skew controlled CMOS outputs SDRAM0:17
• Supports four SDRAM DIMMs
• Ideal for high-performance systems designed around
440BX chip set
• SMBus serial configuration interface
• Output skew between any two outputs is less than
250 ps
• 1 to 5 ns propagation delay
• DC to 133-MHz operation
• Single 3.3V supply voltage
• Low power CMOS design packaged in a 48-pin SSOP

Small Shrink Outline Package

Overview

The Cypress W40S01-04 is a low-voltage, eighteen-output signal buffer. Output buffer impedance is approximately which is ideal for driving SDRAM DIMMs.

Block Diagram

SDRAM Buffer - 4 DIMM

Key Specifications

Supply VDDQ3 = 3.3V ± 5% Operating 0°C to +70°C Input Threshold 1.5V typical Maximum Input Voltage ...................................VDDQ3 + 0.5V Input 0 to 133 MHz BUF_IN to SDRAM0:17 Propagation Delay to ns Output Edge V/ns Output Skew ±250 ps Output Duty Cycle 45/55% worst case Output typical Output Type CMOS rail-to-rail Part to Part ps

Pin Configuration

SDATA SCLOCK

Serial Port

Device Control

BUF_IN

OE SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 SDRAM9 SDRAM10 SDRAM11 SDRAM12 SDRAM13 SDRAM14 SDRAM15 SDRAM16 SDRAM17

NC VDDQ3 SDRAM0 SDRAM1 GND VDDQ3 SDRAM2 SDRAM3 GND BUF_IN VDDQ3 SDRAM4 SDRAM5 GND VDDQ3 SDRAM6 SDRAM7 GND VDDQ3 SDRAM16 GND VDDQ3 SDATA [1]

SSOP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 NC
47 NC
46 VDDQ3
45 SDRAM15
44 SDRAM14
43 GND
42 VDDQ3
41 SDRAM13
40 SDRAM12
39 GND 38 OE[1]
37 VDDQ3
36 SDRAM11
35 SDRAM10
34 GND
33 VDDQ3
32 SDRAM9
31 SDRAM8
30 GND
29 VDDQ3
28 SDRAM17
Ordering Information
Ordering Code W40S01

Freq. Mask Code

Document # 38-00811-*A

Package Name

Package Type 48-pin SSOP 300 mils

Layout Example
+3.3V Supply

SDATA
1G 2 3V 4G
6G 7V 8G 9
10 11 G 12 V
13 G 14 15 G 16 V 17 G 18 19 G 20 V
21 G 22 23 V 24 G

W40S01-04

W40S01-04

G 48 47

V 46 G 45

G 43 V 42 G 41
40 39 G 38 V 37

G 36 35

G 34 V 33 G 32
31 G 30 V 29

G 28 27 26

SCLOCK

C = µF G = VIA to GND plane layer V =VIA to supply plane layer

Package Diagram
48-Pin Shrink Small Outline Package SSOP, inch

W40S01-04

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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Datasheet ID: W40S01-04H 508354