PEX8747-BA80BFBC G

PEX8747-BA80BFBC G Datasheet

PEX 8747, PCI Express Gen 3 Switch, 48 Lanes, 5 Ports

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PEX8747-BA80BFBC G	PEX8747-BA80BFBC G (pdf)

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PEX 8747, PCI Express Gen 3 Switch, 48 Lanes, 5 Ports Highlights PEX 8747 General Features o 48-lane, 5-port PCIe Gen 3 switch - Integrated GT/s SerDes o 27 x 27mm2, 676-pin FCBGA package o Typical Power Watts PEX 8747 Key Features o Standards Compliant - PCI Express Base Specification, r3.0 compatible w/ PCIe r1.0a/1.1 & - PCI Power Management Spec, r1.2 - Microsoft Vista Compliant - Supports Access Control Services - Dynamic link-width control - Dynamic SerDes speed control o High Performance performancePAK 9 Read Pacing bandwidth throttling 9 Multicast 9 Dynamic Buffer/FC Credit Pool - Non-blocking switch fabric - Full line rate on all ports - Packet Cut-Thru with 100ns max packet latency x16 to x16 - 2KB Max Payload Size o Quality of Service QoS - Eight traffic classes per port - Weighted round-robin source port arbitration o Reliability, Availability, Serviceability visionPAK 9 Per Port Performance Monitoring Per port payload & header counters 9 SerDes Eye Capture 9 PCIe Packet Generator 9 Error Injection and Loopback - All ports hot plug capable thru I2C Hot Plug Controller on every port - ECRC and Poison bit support - Data Path parity - Memory RAM Error Correction - INTA# and FATAL_ERR# signals - Advanced Error Reporting - Port Status bits and GPIO available • Per port error diagnostics - JTAG AC/DC boundary scan The ExpressLane PEX 8747 device offers Multi-Host PCI Express switching capability enabling users to connect a host to its respective endpoints via scalable, high bandwidth, non-blocking interconnection to a variety of graphics applications. The PEX 8747 is optimized to support high-resolution graphics while supporting peer-to-peer traffic and multicast for maximum performance. High Performance & Low Packet Latency The PEX 8747 architecture supports packet cut-thru with a maximum latency of 100ns x16 to x16 . This, combined with large packet memory, flexible common buffer/FC credit pool and non-blocking internal switch architecture, provides full line rate on all ports for performance-hungry applications such as servers and switch fabrics. The low latency enables applications to achieve high throughput and performance. In addition to low latency, the device supports a packet payload size of up to 2048 bytes, enabling the user to achieve even higher throughput. Data Integrity The PEX 8747 provides end-to-end CRC ECRC protection and Poison bit support to enable designs that require end-to-end data integrity. PLX also supports data path parity and memory RAM error correction circuitry throughout the internal data paths as packets pass through the switch. Flexible Configuration The PEX 8747’s 5 ports can be configured to lane widths of x8 or x16. Flexible buffer allocation, along with the device's flexible packet flow control, maximizes throughput for applications where more traffic flows in the downstream, rather than upstream, direction. Any port can be designated as the upstream port, which can be changed dynamically. Figure 1 shows some of the PEX 8747’s common port configurations. PEX 8747 PEX 8747 x16 x8 x16 PEX 8747 x8 Figure Common Port Configurations SerDes Power and Signal Management The PEX 8747 provides low power capability that is fully compliant with the PCIe power management specification and supports software control of the SerDes outputs to allow optimization of power and signal strength in a system. Furthermore, the SerDes block supports loop-back modes and advanced reporting of error conditions, which enables efficient management of the entire system. PLX Technology, 10/20/2010, Version PEX 8747, PCI Express Gen 3 Switch, 48 Lanes, 5 Ports Interoperability performancePAK Exclusive to PLX, performancePAK is a suite of unique and innovative performance features which allows PLX’s Gen 2 switches to be the highest performing Gen 2 switches in the market today. The performancePAK features consists of the Read Pacing, Multicast, and Dynamic Buffer Pool. Read Pacing The Read Pacing feature allows users to throttle the amount of read requests being made by downstream devices. When a downstream device requests several long reads back-to-back, the Root Complex gets tied up in serving that downstream port. If that port has a narrow link and is therefore slow in receiving these read packets from the Root Complex, then other downstream ports may become starved thus, impacting performance. The Read Pacing feature enhances performances by allowing for the adequate servicing of all downstream devices. Multicast The Multicast feature enables the copying of data packets from one ingress port to multiple up to 4 egress ports in one transaction allowing for higher performance in dualgraphics, storage, security, and redundant applications, among others. Multicast relieves the CPU from having to conduct multiple redundant transactions, resulting in higher system performance. Dynamic Buffer Pool The PEX 8747 employs a dynamic buffer pool for Flow Control FC management. As opposed to a static buffer scheme which assigns fixed, static buffers to each port, PLX’s dynamic buffer allocation scheme utilizes a common pool of FC Credits which are shared by other ports. This shared buffer pool is fully programmable by the user, so FC credits can be allocated among the ports as needed. Not only does this prevent wasted buffers and inappropriate buffer assignments, any unallocated buffers remain in the common buffer pool and can then be used for faster FC credit updates. visionPAK Another PLX exclusive, visionPAK is a debug diagnostics suite of integrated hardware and software instruments that users can use to help bring their systems to market faster. visionPAK features consist of Performance Monitoring, SerDes Eye Capture, Error Injection, SerDes Loopback, and more. Performance Monitoring The PEX 8747’s real time performance monitoring allows users to literally “see” ingress and egress performance on each port as traffic passes through the switch using PLX’s Software Development Kit SDK . The monitoring is completely passive and therefore has no affect on overall system performance. Internal counters provide extensive granularity down to traffic & packet type and even allows for the filtering of traffic i.e. count only Memory Writes . SerDes Eye Capture Users can evaluate their system’s signal integrity at the physical layer using the PEX 8747’s SerDes Eye Capture feature. Using PLX’s SDK, users can view the receiver eye of any lane on the switch. Users can then modify SerDes settings and see the impact on the receiver eye. Figure 2 shows a screenshot of the SerDes Eye Capture feature in the SDK. Figure SerDes Eye Capture Product Ordering Information PEX8747-AA80BC G 48-Lane, 5-Port PCI Express Switch, Pb-Free 27x27mm2 PEX8747-AA RDK PEX 8747 Rapid Development Kit PLX Technology, Inc. All rights reserved. PLX, the PLX logo, ExpressLane, Read Pacing and Dual Cast are trademarks of PLX Technology, Inc. All other product names that appear in this material are for identification purposes only and are acknowledged to be trademarks or registered trademarks of their respective companies. Information supplied by PLX is believed to be accurate and reliable, but PLX assumes no responsibility for any errors that may appear in this material. PLX reserves the right, without notice, to make changes in product design or specification. Visit for more information. Figure PEX 8747 RDK Development Tools PLX offers hardware and software tools to enable rapid customer design activity. These tools consist of a hardware module PEX 8747 RDK , hardware documentation available at and a Software Development Kit also available at PLX Technology, 10/20/2010, Version

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PEX 8747, PCI Express Gen 3 Switch, 48 Lanes, 5 Ports

Highlights

PEX 8747 General Features
o 48-lane, 5-port PCIe Gen 3 switch - Integrated GT/s SerDes
o 27 x 27mm2, 676-pin FCBGA package o Typical Power Watts

PEX 8747 Key Features
o Standards Compliant - PCI Express Base Specification, r3.0 compatible w/ PCIe r1.0a/1.1 & - PCI Power Management Spec, r1.2 - Microsoft Vista Compliant - Supports Access Control Services - Dynamic link-width control - Dynamic SerDes speed control
o High Performance performancePAK 9 Read Pacing bandwidth throttling 9 Multicast 9 Dynamic Buffer/FC Credit Pool - Non-blocking switch fabric - Full line rate on all ports - Packet Cut-Thru with 100ns max packet latency x16 to x16 - 2KB Max Payload Size
o Quality of Service QoS - Eight traffic classes per port - Weighted round-robin source port arbitration
o Reliability, Availability, Serviceability visionPAK 9 Per Port Performance Monitoring Per port payload & header counters 9 SerDes Eye Capture 9 PCIe Packet Generator 9 Error Injection and Loopback - All ports hot plug capable thru I2C Hot Plug Controller on every port - ECRC and Poison bit support - Data Path parity - Memory RAM Error Correction - INTA# and FATAL_ERR# signals - Advanced Error Reporting - Port Status bits and GPIO available
• Per port error diagnostics - JTAG AC/DC boundary scan

The ExpressLane PEX 8747 device offers Multi-Host PCI Express switching capability enabling users to connect a host to its respective endpoints via scalable, high bandwidth, non-blocking interconnection to a variety of graphics applications. The PEX 8747 is optimized to support high-resolution graphics while supporting peer-to-peer traffic and multicast for maximum performance.

High Performance & Low Packet Latency The PEX 8747 architecture supports packet cut-thru with a maximum latency of 100ns x16 to x16 . This, combined with large packet memory, flexible common buffer/FC credit pool and non-blocking internal switch architecture, provides full line rate on all ports for performance-hungry applications such as servers and switch fabrics. The low latency enables applications to achieve high throughput and performance. In addition to low latency, the device supports a packet payload size of up to 2048 bytes, enabling the user to achieve even higher throughput.

Data Integrity The PEX 8747 provides end-to-end CRC ECRC protection and Poison bit support to enable designs that require end-to-end data integrity. PLX also supports data path parity and memory RAM error correction circuitry throughout the internal data paths as packets pass through the switch.

Flexible Configuration The PEX 8747’s 5 ports can be configured to lane widths of x8 or x16. Flexible buffer allocation, along with the device's flexible packet flow control, maximizes throughput for applications where more traffic flows in the downstream, rather than upstream, direction. Any port can be designated as the upstream port, which can be changed dynamically. Figure 1 shows some of the PEX 8747’s common port configurations.

PEX 8747

PEX 8747
x16 x8 x16

PEX 8747
x8 Figure Common Port Configurations

SerDes Power and Signal Management

The PEX 8747 provides low power capability that is fully compliant with the PCIe power management specification and supports software control of the SerDes outputs to allow optimization of power and signal strength in a system. Furthermore, the SerDes block supports loop-back modes and advanced reporting of error conditions, which enables efficient management of the entire system.

PLX Technology,
10/20/2010, Version

PEX 8747, PCI Express Gen 3 Switch, 48 Lanes, 5 Ports

Interoperability
performancePAK

Exclusive to PLX, performancePAK is a suite of unique and innovative performance features which allows PLX’s Gen 2 switches to be the highest performing Gen 2 switches in the market today. The performancePAK features consists of the Read Pacing, Multicast, and Dynamic Buffer Pool.

Read Pacing

The Read Pacing feature allows users to throttle the amount of read requests being made by downstream devices. When a downstream device requests several long reads back-to-back, the Root Complex gets tied up in serving that downstream port. If that port has a narrow link and is therefore slow in receiving these read packets from the Root Complex, then other downstream ports may become starved thus, impacting performance. The Read Pacing feature enhances performances by allowing for the adequate servicing of all downstream devices.

Multicast

The Multicast feature enables the copying of data packets from one ingress port to multiple up to 4 egress ports in one transaction allowing for higher performance in dualgraphics, storage, security, and redundant applications, among others. Multicast relieves the CPU from having to conduct multiple redundant transactions, resulting in higher system performance.

Dynamic Buffer Pool

The PEX 8747 employs a dynamic buffer pool for Flow Control FC management. As opposed to a static buffer scheme which assigns fixed, static buffers to each port, PLX’s dynamic buffer allocation scheme utilizes a common pool of FC Credits which are shared by other ports. This shared buffer pool is fully programmable by the user, so FC credits can be allocated among the ports as needed. Not only does this prevent wasted buffers and inappropriate buffer assignments, any unallocated buffers
remain in the common buffer pool and can then be used for faster FC credit updates.
visionPAK

Another PLX exclusive, visionPAK is a debug diagnostics suite of integrated hardware and software instruments that users can use to help bring their systems to market faster. visionPAK features consist of Performance Monitoring, SerDes Eye Capture, Error Injection, SerDes Loopback, and more.

Performance Monitoring

The PEX 8747’s real time performance monitoring allows users to literally “see” ingress and egress performance on each port as traffic passes through the switch using PLX’s Software Development Kit SDK . The monitoring is completely passive and therefore has no affect on overall system performance. Internal counters provide extensive granularity down to traffic & packet type and even allows for the filtering of traffic i.e. count only Memory Writes .

SerDes Eye Capture

Users can evaluate their system’s signal integrity at the physical layer using the PEX 8747’s SerDes Eye Capture feature. Using PLX’s SDK, users can view the receiver eye of any lane on the switch. Users can then modify SerDes settings and see the impact on the receiver eye. Figure 2 shows a screenshot of the SerDes Eye Capture feature in the SDK.

Figure SerDes Eye Capture
Product Ordering Information

PEX8747-AA80BC G
48-Lane, 5-Port PCI Express Switch, Pb-Free 27x27mm2

PEX8747-AA RDK

PEX 8747 Rapid Development Kit

PLX Technology, Inc. All rights reserved. PLX, the PLX logo, ExpressLane, Read Pacing and Dual Cast are trademarks of PLX Technology, Inc. All other product names that appear in this material are for identification purposes only and are acknowledged to be trademarks or registered trademarks of their respective companies. Information supplied by PLX is believed to be accurate and reliable, but PLX assumes no responsibility for any errors that may appear in this material. PLX reserves the right, without notice, to make changes in product design or specification.

Visit for more information.

Figure PEX 8747 RDK

Development Tools

PLX offers hardware and software tools to enable rapid customer design activity. These tools consist of a hardware module PEX 8747 RDK , hardware documentation available at and a Software Development Kit also available at

PLX Technology,
10/20/2010, Version

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived PEX8747-BA80BFBC G Datasheet file may be downloaded here without warranties.

Datasheet ID: PEX8747-BA80BFBC G 520516