PEX8114-BC13BI

PEX8114-BC13BI Datasheet


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PCI Express-to-PCI/PCI-X Bridge Data Book

Version September 2010

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Copyright Information

Copyright 2006 2010 PLX Technology, Inc. All Rights Reserved. The information in this document is proprietary to PLX Technology. No part of this document may be reproduced in any form or by any means or used to make any derivative work such as translation, transformation, or adaptation without written permission from PLX Technology.

PLX Technology provides this documentation without warranty, term or condition of any kind, either express or implied, including, but not limited to, express and implied warranties of merchantability, fitness for a particular purpose, and non-infringement. While the information contained herein is believed to be accurate, such information is preliminary, and no representations or warranties of accuracy or completeness are made. In no event will PLX Technology be liable for damages arising directly or indirectly from any use of or reliance upon the information contained in this document. PLX Technology may make improvements or changes in the product s and/or the program s described in this documentation at any time.

PLX Technology retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX Technology assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX Technology products.

PLX Technology and the PLX logo are registered trademarks and ExpressLane is a trademark of PLX Technology, Inc.

PCI Express is a trademark of the PCI Special Interest Group PCI-SIG .

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Document Number 8114-BC/BD-SIL-DB-P1-3.2

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Version

Description of Changes

June, 2006

August, 2006

December, 2006

Applied miscellaneous corrections and enhancements throughout the data book.

February, 2008

Rewrote Chapters 1, 3, 12, and 15, and applied many updates to Chapter

Reorganized Tables 2-10 and

Renamed Chapter 17 to “Thermal and Mechanical Specifications.” As a result, Table 17-1 is now Table 17-2, and Table 17-2 is now Table Added Note d to Table

Added new “Power Characteristics” section to Chapter 16 Section and renumbered all subsequent sections accordingly.

Changed minimum serial EEPROM size referenced in Section

Updated Tables 15-2 and

Changed minimum storage temperature.

Applied miscellaneous corrections and enhancements throughout the data book.

Added solder mask opening information to Table

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The information contained in this document is subject to change without notice. This document is periodically updated as new information is made available.

Audience
C.1 Product Ordering Information 349 C.2 United States and International Representatives and Distributors 350 C.3 Technical Support 350

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Contents

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Registers

Power Management Capability Registers 230 40h Power Management Capability 44h Power Management Status and Control

Message Signaled Interrupt Capability Registers 233 48h Message Signaled Interrupt Capability 4Ch MSI Address 50h MSI Upper Address 54h MSI Data

PCI-X Capability Registers 235 58h PCI-X Capability, Secondary Status 5Ch PCI-X Bridge Status 60h Upstream Split Transaction Control 64h Downstream Split Transaction Control.

PCI Express Capability Registers 242 68h PCI Express Capability List and Capability 6Ch Device Capability 70h Device Status and Control 74h Link Capability 78h Link Status and Control 7Ch Slot Capability 80h Slot Status and Control

Device-Specific Indirect Configuration Mechanism Registers 257 F8h Configuration Address Window FCh Configuration Data Window

Device Serial Number Extended Capability Registers 258 100h Device Serial Number Extended Capability. 104h Serial Number Lower DW 108h Serial Number Higher DW .

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Power Budget Extended Capability Registers 259 138h Power Budget Extended Capability 259 13Ch Data Select 259 140h Power Budget Data. 260 144h Power Budget Capability 260

Virtual Channel Extended Capability Registers. 261 148h Virtual Channel Extended Capability 261 14Ch Port VC Capability 262 150h Port VC Capability 2 262 154h Port VC Status and Control 263 158h VC0 Resource Capability 263 15Ch VC0 Resource Control 264 160h VC0 Resource Status 264

Device-Specific Registers 265

Device-Specific Registers Error Checking and Debug 266 1C8h ECC Check Disable 267 1CCh Device-Specific Error 32-Bit Error Status 268 1D0h Device-Specific Error 32-Bit Error Mask 270 1E0h Power Management Hot Plug User Configuration 272 1E4h Egress Control and Status 273 1E8h Bad TLP Count. 274 1ECh Bad DLLP Count 274 1F0h TLP Payload Length Count 274 1F8h ACK Transmission Latency Limit 274

Device-Specific Registers Physical Layer. 275 210h Phy User Test Pattern 0 276 214h Phy User Test Pattern 1 276 218h Phy User Test Pattern 2 276 21Ch Phy User Test Pattern 3 276 220h Physical Layer Command and Status. 277 224h Port Configuration. 277 228h Physical Layer Test 278 230h Physical Layer Port Command 280 234h SKIP Ordered-Set Interval 280 238h SerDes[0-3] Quad Diagnostics Data 281 248h SerDes Nominal Drive Current Select 281 24Ch SerDes Drive Current Level 1 281 254h SerDes Drive Equalization Level Select 1 282 260h Serial EEPROM Status and Control 283 264h Serial EEPROM Buffer 285

Device-Specific Registers Content-Addressable Memory Routing 286

Device-Specific Registers Bus Number CAM 287 2E8h Bus Number CAM 8 287

Device-Specific Registers I/O CAM 287 318h I/O CAM_8 287

Device-Specific Registers Address-Mapping CAM 288 3C8h AMCAM_8 Memory Limit and Base. 288 3CCh AMCAM_8 Prefetchable Memory Limit and Base[31:0] 288 3D0h AMCAM_8 Prefetchable Memory Base[63:32] 288 3D4h AMCAM_8 Prefetchable Memory Limit[63:32] 288

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Registers

Device-Specific Registers Transaction Layer Ingress Control 289 660h TIC Control 668h TIC Port Enable

Device-Specific Register I/O CAM Base and Limit Upper 16 Bits 289 6A0h I/OCAM_8 Base and Limit Upper 16 Bits

Device-Specific Registers Base Address Shadow 291 700h BAR0_8 704h BAR1_8

Device-Specific Registers Ingress Credit Handler 292 9F4h INCH FC Update Pending Timer 9FCh INCH Mode

Ingress Credit Handler Threshold Virtual Channel Registers 293 A00h INCH Threshold VC0 Posted A04h INCH Threshold VC0 Non-Posted. A08h INCH Threshold VC0 Completion

Internal Credit Handler Virtual Channel and Type Threshold Registers 294

ITCH VC&T Threshold Registers PCI Express Interface Device-Specific 294
PCI-X-Specific Registers 303 FA0h PCI Clock Enable, Strong Ordering, Read Cycle Value FA4h Prefetch

PCI Arbiter Registers 306 FA8h Arbiter FACh Arbiter 1 FB0h Arbiter 2

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Advanced Error Reporting Capability Registers 307 FB4h PCI Express Enhanced Capability Header 308 FB8h Uncorrectable Error Status 308 FBCh Uncorrectable Error Mask 309 FC0h Uncorrectable Error Severity 310 FC4h Correctable Error Status 311 FC8h Correctable Error Mask 311 FCCh Advanced Error Capabilities and Control 312 FD0h Header Log_0 312 FD4h Header Log_1 312 FD8h Header Log_2 312 FDCh Header Log_3 312 FE0h Secondary Uncorrectable Error Status 313 FE4h Secondary Uncorrectable Error Mask 314 FE8h Secondary Uncorrectable Error Severity 316 FECh Secondary Uncorrectable Error Pointer. 317 FF0h FFCh Secondary Header Log 317

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Chapter 1 Introduction
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Introduction

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• Package 17 x 17 mm2, 256-ball Plastic Ball Grid Array PBGA package Typical power 1.67W JTAG
• SPI/serial EEPROM for initialization
• Compliant to the following specifications:

PCI Express-to-PCI/PCI-X Bridge r1.0 IEEE Standard IEEE Standard Test Access Port and Boundary-Scan

Architecture, 1990 IEEE Standard IEEE Standard 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan

Architecture IEEE Standard IEEE Standard 1149.1b-1994, Specifications for Vendor-Specific Extensions

IEEE Standard IEEE Standard Test Access Port and Boundary-Scan Architecture Extensions

IEEE Standard

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PCI Express to PCI/PCI-X Bridge

PCI Express to PCI/PCI-X Bridge

The PEX 8114 is a high-performance bridge that enables designers to migrate Conventional PCI and PCI-X Bus interfaces to the new advanced serial PCI Express protocol with an economical single-chip solution. This simple two-port device is equipped with a standard PCI Express port that scales to x1, x2, or x4 lanes in width, giving an effective bit rate scaling from to 10 Gbps. Using LVDS PCI Express signaling, this bandwidth is achieved with the lowest possible ball count 16 balls for four lanes .

The single parallel bus segment supports either Conventional PCI or the advanced PCI-X protocol. Using a 64-bit wide parallel data path at a clock frequency of 133 MHz, PCI-X can achieve a maximum bandwidth of 8 Gbps. In order to optimize throughput and traffic flow between the two bus protocols, the PEX 8114 supports internal queues with Flow Control FC features.

The PEX 8114 is available in a standard 256-ball Plastic Ball Grid Array PBGA package. The small footprint and low-power consumption make the PEX 8114 an ideal bridge for use on adapter boards, daughter boards, add-on modules, and backplane designs, as well as on larger planar boards.

Figure PEX 8114 Two-Port Device

PCI/PCI-X Bus Segment

PEX 81104

PCI Express Link

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Introduction

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Introduction to PEX 8114 Operation

The PEX 8114 is a PCI Express-to-PCI-X bridge that provides a functional link from a PCI or PCI-X Bus segment to a PCI Express port. The PCI Express port functions as a single port, and may not be bifurcated into multiple ports. The port can be configured as x1, x2, or x4 lanes, each operating at Gbps. The SerDes and all associated circuitry are integrated into each lane, thus the PEX 8114 requires no external interface components. The PCI Express port conforms to the PCI Express r1.0a.
• Forward Transparent bridge - the Host resides on the PCI Express side of the bridge, and Configuration accesses originate in the PCI Express Root Complex

Figure 1-2 provides a PEX 8114 top-level block diagram.

Figure PEX 8114 Top-Level Block Diagram

Hot Plug PCI Express Client only

Serial EEPROM

PCI or PCI-X Bus Segment

Power Management

PCI 4-Input Arbiter

PCI/PCI-X Bus
25, 33, 50, 66, 100, 133 MHz

PCI/PCI-X Module

PEX 8114
The PEX 8114 supports Data transfers from the PCI-X port to the PCI Express port. The PCI-X port operates in PCI or PCI-X mode, at clock rates up to 133 MHz and 32- or 64-bit bus widths. The PCI Express port is four lanes wide, and can be configured as a 1-, 2-, or 4-lane port. The PEX 8114 internal data path is based upon a central RAM. which holds and orders all data transferred through the bridge in three separate linked lists including Posted, Non-Posted and Completion data. There is a separate, central 8-KB RAM for data flowing in each direction. All transactions are held within the RAM in a double store-and-forward method. Separate link lists for Posted and Non-Posted transactions, as well as Completions, share space within the RAM and all link list accesses to the internal RAM output are governed, according to PCI Express Ordering rules. At least 2 KB of the 8-KB RAM are dedicated to Completions. Completions can optionally require as much as 6 KB of memory, according to demand. The remainder of the RAM is used for Posted and Non-Posted requests, or remains empty. In addition to the central RAM, there are eight, 256-byte buffers in the PCI modules that track and combine the data for up to eight concurrent Non-Posted PCI requests with their Completion data when the Completion returns from the PCI Express link. Refer to Chapter 7, “Bridge Operations,” for further details. Additionally, the PCI interface modules include eight data-holding register sets that are dedicated to tracking the Completion progress of eight PCI Express requests on the PCI Bus. These registers hold information that uniquely identifies the Target location and data quantity requested, for up to eight PCI Express requests. As the PCI module’s state machines supply the data requested by the PCI Express device, these registers track progress toward Completion. After a transaction completes, the internal resources dedicated to that transaction are recovered and readied to service a new transaction.

PCI Express Credits

PCI Express credits are issued according to the PCI Express requirements to manage the internal 8-KB central RAM and ensure that no internal memory linked list is overrun.

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Latency and Bandwidth

The PEX 8114 can be configured as a PCI or PCI-X device at up to 133 MHz and 64-bit data bus on the PCI-X side, transacting data with the PCI Express port configured as a 1-, 2-, or 4-lane port x1, x2, or x4, respectively . It is anticipated that from a bandwidth-balancing perspective, the PCI Express port configured as a 4-lane device matches well with the PCI-X side operating at 133 MHz and 64 bits. In this matched configuration, expect full bandwidth utilization on the PCI Express lanes and PCI-X Bus, with throughput limitations being the external PCI Express and PCI-X ports’ bandwidth capability and not the PEX 8114’s internal bandwidth. A 66-MHz, 64-bit PCI-X port should match a x2 PCI Express port. It is anticipated that the PEX 8114 does not limit the bandwidth of those transactions. Bandwidth is affected by many parameters, including but not limited to arbitration latency, cycle startup latency, Retries, packet sizes, and external endpoint latency. Adjust the parameters within the PEX 8114, based upon the PCI Express-to-PCI/PCI-X Bridge r1.0.

Data Flow-Through Latency

When the PEX 8114 is configured as a PCI-X device, operating at 133-MHz clock frequency with a 64-bit wide data bus, and the PCI Express port is configured as a 4-lane link, expect approximately 300 ns latency through the PEX 8114 for Header-only packets and approximately 850 ns for Headers with 256-byte Data packets. This is the latency of data driven from PCI-X to PCI Express. This latency is measured from the frame drop on the PCI-X Bus, when data is driven into the PEX 8114, until the starting symbol of data TLP appears on the PCI Express lanes. Internal latency of data driven from PCI Express to PCI-X is similar.

PCI Transaction Initial Latency and Cycle Recovery Time

In PCI mode, when the PEX 8114 is a Read Cycle Target, the PEX 8114 supplies data or Retries the Master Read request. There are eight Clock cycles from when the Master asserts PCI_FRAME# until the PEX 8114 signals a Retry or is ready to supply data. This equates to an initial target latency of 8 clocks.

When the PEX 8114 is the Write Cycle Master, there is one Clock cycle from when the Master drives PCI_FRAME# until the PEX 8114 drives PCI_IRDY# ready to supply data. This cycle is the Address phase, required by the PCI r3.0. There are no initial wait states added by the PEX The PEX 8114 is a slow-decode device and supports fast back-to-back addressing.

The PEX 8114 requires certain Clock cycles after completion of a previous transaction before it can participate in another transaction. This period is comprised of the Clock cycles from the last Data phase of the preceding transaction until PCI_FRAME# is asserted on a new transaction, and is referred to as transaction cycle recovery time. The cycle recover time from mastering a PCI-X transaction is 10 Clock cycles.

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PCI-X Transaction Initial Latency and Cycle Recovery Time

PCI-X Transaction Initial Latency and Cycle Recovery Time

In PCI-X mode, when the PEX 8114 is a Read Transaction Target, there are seven Clock cycles from when the Master asserts PCI_FRAME# until the PEX 8114 drives a Split Response to the PCI-X Read request. When the PEX 8114 is a PCI-X Write Cycle Target, there are seven Clock cycles from when the Master asserts PCI_FRAME# until the PEX 8114 drives PCI_IRDY# ready to accept data. This equates to an initial Target latency of 2 clocks.

When the PEX 8114 is a Write or Read Completion Master, there are three Clock cycles from when the PEX 8114 asserts PCI_FRAME# until the PEX 8114 asserts PCI_IRDY# indicating that it is ready to drive data. These three Clocks cycles are the Address, Attribute, and Turnaround cycles required by the PCI-X r2.0a. There are no initial wait states added by the PEX The PEX 8114 is a slow-decode device and supports fast back-to-back addressing.

The PEX 8114 requires certain Clock cycles after the completion of a previous transaction, before it can participate in another transaction. This period is comprised of the Clock cycles from the last Data phase of the preceding transaction until PCI_FRAME# is asserted on a new transaction, and is referred to as transaction cycle recovery time. The cycle recover time for mastering a PCI cycle is seven Clock cycles.

Arbitration Latency

Arbitration latency is the number of PCI Clock cycles required for the bridge to be granted the bus when it is waiting to make a transfer. This time can vary and is a function of the number of devices on the PCI Bus and each device’s demand for bus control. At a minimum, the bus can be parked on the bridge and in that case, the arbitration latency is 0 clocks. If the bus is not parked on the bridge and not being used by another device, the latency is 1 clock after the request. If the bus is being used by another Master and hidden arbitration is enabled, the arbitration latency is 1 clock after the other users relinquish the bus. If the bus is being used by another Master and hidden arbitration is not enabled, the arbitration latency is 2 clocks after the other users relinquish the bus.

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Chapter 5 Address Spaces

Introduction

This chapter discusses the PEX 8114 Address spaces.

Supported Address Spaces

The PEX 8114 supports the following Address spaces
• Conventional PCI-compatible Configuration 00h to FFh 256 bytes
• PCI Express Extended Configuration 100h to FFFh
• I/O 32-bit includes ISA and VGA modes
• Memory-Mapped I/O 32-bit non-prefetchable
• Prefetchable memory 64-bit
• Base Address register BAR access to internal registers

Configuration registers set up for I/O, Memory-Mapped and Prefetchable Memory Address spaces determine which transactions are forwarded from the primary bus to the secondary bus and from the secondary bus to the primary bus. The I/O and Memory ranges are defined by a set of Base and Limit registers in the Configuration Header. Transactions falling within the ranges defined by the Base and Limit registers are forwarded from the primary bus to the secondary bus. Transactions falling outside these ranges are forwarded from the secondary bus to the primary bus.

Table 5-1 defines the primary and secondary interfaces for the two PEX 8114 Bridge modes.

Table Bridge Mode Primary and Secondary Interfaces

Primary Interface/Bus PCI Express PCI
The PEX 8114 complies with the following specifications for the listed processes and modes
• PCI r3.0 PCI mode
• PCI-X r1.0b or PCI-X r2.0a PCI-X mode
• PCI Express r1.0a PCI Express port
• PCI Express-to-PCI/PCI-X Bridge r1.0 PCI and PCI Express Transaction Ordering rules

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PCI-to-PCI Express Transactions

When a PCI device attempts a Write from the PCI Bus to the PCI Express interface, the PEX 8114 translates PCI Burst Write transactions into PCI Express data TLPs. In the most basic transaction, the PEX 8114 receives a Data burst on the PCI Bus and transfers the data into a PCI Express TLP.

PCI-to-PCI Express Flow Control

The PEX 8114 ensures that the internal resources for storing data are not overrun. If an internal data storage resource is full, or approaching full in certain cases, the PEX 8114 issues Retries to all new Request transactions and only accepts Completions or requests of types without depleted resources.

PCI-to-PCI Express PCI Posted Write Requests

When servicing Posted Writes, no Completion information is returned to the PCI device that originated the transaction, and when the TLP is transmitted to the PCI Express link, the transaction is considered complete. Table 7-1 defines PCI Posted Write requests and the resultant PCI Express transactions created in response to the Posted Write.

Table PCI Posted Write Requests

Initial Posted PCI Transactions Interrupt ACK Special Cycle Dual Address Cycle Memory Write Memory Write and Invalidate

Resultant PCI Express Transaction Not supported Not supported MWr TLP, up to Maximum Packet Size fmt=11b MWr TLP, up to Maximum Packet Size fmt=1Xb MWr TLP, up to Maximum Packet Size fmt=1Xb

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PCI-to-PCI Express PCI Non-Posted Requests

PCI-to-PCI Express PCI Non-Posted Requests

On Non-Posted PCI transactions, the PEX 8114 issues a Retry to the PCI originator when it receives the first request. The Retry indicates that the Non-Posted transaction was not completed on the PCI Express port. In addition to transmitting the Retry in response to the first Non-Posted PCI request, the PEX 8114 also creates and issues a Non-Posted TLP on the PCI Express link. Table 7-2 defines all Non-Posted requests and their resultant PCI Express requests. Direct Non-Posted transactions to Prefetchable or Non-Prefetchable Memory space.

Table PCI Non-Posted Requests

Initial Non-Posted PCI Transactions

I/O Write I/O Read Memory Read Configuration Write Configuration Read Configuration Type 1 Write Configuration Type 1 Read Dual Address Cycle Memory Read Line Memory Read Line Multiple

Resultant PCI Express Transaction

IOwr TLP length=1 type=0010b, fmt=10b IOrd TLP length=1 type=0010b, fmt=00b MemRd TLP, up to Prefetch Size type=0000b, fmt=0Xb CfgWr0/1 TLP length=1 type=00100b, fmt=10b CfgRd0/1 TLP length=1 type=00100b, fmt=00b CfgWr1 TLP length=1 type=00100b, fmt=10b CfgRd1 TLP length=1 type=00100b, fmt=00b fmt=01b for Memory Reads and Memory Writes MemRd TLP, up to Cache Line Size fmt=1Xb One or more MemRd TLP, up to Cache Line Size type=0000b, fmt=1Xb

Note “X” indicates “Don’t Care.”

PCI-to-PCI Express PCI Non-Posted Transactions until PCI Express Completion Returns

After the initial Non-Posted request that caused the resultant transaction is issued on the PCI Express interface, subsequent requests from the PCI device are Retried until the PEX 8114 detects that the PCI Express link transmitted a Completion TLP matching the request. The PEX 8114 supports up to eight parallel Non-Posted requests. If the internal state machines indicate that the link is down, and the Bridge Control register Master Abort Mode bit is set offset 3Ch[21]=1 , the PEX 8114 replies to the PCI Requester’s follow-on Non-Posted requests with a Target Abort. If the Master Abort Mode bit is cleared offset 3Ch[21]=0 , the PEX 8114 replies to the PCI Requester’s follow-on Non-Posted requests with FFFF_FFFFh.

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PCI-to-PCI Express PCI Requests Do Not Contain Predetermined Lengths

PCI Read requests do not contain an indication of the quantity of data they require however, the TLPs that the PEX 8114 issues to the PCI Express device must indicate Data request quantities. The PEX 8114 treats Memory Reads to Prefetchable space differently than it treats Memory Reads to Non-Prefetchable space, and differently than it treats Memory Read Lines and Memory Read Line Multiples. The PEX 8114 resolves the Data request quantity ambiguity, as discussed in the following sections.

Memory Read Requests to Non-Prefetchable Space

When the PEX 8114 receives a Memory Read request to Non-Prefetchable Memory space, it generates a PCI Express Read request for 1 DWord, if the system is running a 32-bit bus, and 2 DWords, if the system is running a 64-bit bus.

Memory Read Requests to Prefetchable Space

When the PEX 8114 receives a Memory Read Request to Prefetchable Memory space in PCI mode, it issues a Read request on the PCI Express interface for an amount of data that is determined by the Prefetch register Prefetch Space Count field offset FA4h[13:8] and the starting address of the request. The Prefetch Space Count field is not used in PCI-X mode because the Request size is provided in the PCI-X Read request. Use of the Prefetch Space Count field to determine Prefetch Size pertains only to PCI mode.

The Prefetch Space Count field specifies the number of DWords to prefetch for Memory Reads originating on the PCI Bus that are forwarded to the PCI Express interface. Only Even values between 0 and 32 are allowed.
• PEX 8114 prefetches 2 DWords when the following conditions are met:

Prefetch Space Count field is cleared to 00h, and
Credits for up to 6 KB of PCI Express Posted and Non-Posted transactions are issued. These transactions are queued, according to PCI Ordering Transaction rules in central memory, and are transmitted to the PCI-X modules as bandwidth allows, limited by the eight outstanding PCI transactions. Transmitting packets into the PCI Express side of the bridge is throttled by space remaining in the central RAM. The process of transmitting transactions onto the PCI Bus is throttled by the number of outstanding transactions transmitted to the PCI endpoints that did not complete. The PEX 8114 supports up to eight outstanding transactions on the PCI Bus. All transactions are driven through the bridge as quickly as possible, limited only by the PCI Express and PCI Bus bandwidths.

PCI Express-to-PCI Express Posted Transactions

When servicing Posted transactions, no Completion information is returned to the PCI Express device that originated the transaction, and when the transaction is transmitted on the PCI Bus, the transaction is considered complete. Table 7-5 defines which PCI Express Posted transactions are supported and to which PCI transaction they are translated.

Table PCI Express Posted Transactions

Initial PCI Express Posted Transaction Type

Memory Write

Message Request

Message Request with Payload

Resultant PCI Transaction

PCI Memory Write.

Messages that cause changes on the PCI side of the bridge are Interrupt messages, which are translated to INTA#. Internally, Power Management and error conditions can cause Error messages to generate to the PCI Express side of the bridge.

Not supported

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PCI Express-to-PCI Express Non-Posted Transactions

When servicing Non-Posted PCI Express transactions, the PEX 8114 accepts the PCI Express TLP and creates and issues a PCI request on the PCI Bus. The necessary data quantity is indicated in the TLP and the PEX 8114 executes as many transactions as required on the PCI Bus to Write or Read the requested data. After the PEX 8114 successfully transmits or receives all data, it issues a Completion TLP to the PCI Express original Requester. The PEX 8114 supports up to eight concurrent Non-Posted PCI requests. Table 7-6 defines the PCI Express Non-Posted requests and the resulting PCI transactions when the Non-Posted PCI Express request is received.

Table PCI Express Non-Posted Transactions

Initial PCI Express Non-Posted Transaction Type

I/O Write Request I/O Read Request Configuration Write Type 0 Configuration Read Type 0 Configuration Write Type 1 Configuration Read Type 1 Memory Read Locked

Memory Read Request

Resultant PCI Transaction

I/O Write I/O Read Configuration Write Type 0 Configuration Read Type 0 Configuration Write Type 1 Configuration Read Type 1 Not supported returns a UR PCI Memory Read, PCI Memory Read Line, or PCI Memory Read Line Multiple

PCI Express-to-PCI Bus Retry
Writes are serially processed on a first-come, first-served basis. Reads are attempted in parallel, that is, if one request receives a disconnect, the PEX 8114 attempts to gather data for another outstanding request, moving from request to request in an effort to complete as many transactions as possible, as soon as possible. If the Force Strong Ordering bit is set offset FA0h[8]=1 , after data is returned in response to a Read request, the PEX 8114 concentrates all requests on gathering the remaining data for that transaction until the transaction completes. By default, the bit is cleared at power-on reset. If the bit is set, only one outstanding Read is allowed at a time. All Posted and Non-Posted Write bursts on the PCI Bus cannot be larger than the PCI Express Maximum Packet Size. There is no internal combining of Write TLPs in an effort to increase the PCI Burst Size.

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PCI Express-to-PCI Transaction Request Size

PCI Express-to-PCI Transaction Request Size

The PEX 8114 determines which type of PCI Read request to issue on the PCI Bus, based upon the size of the PCI Express Read request that the bridge receives. If a PCI Express Memory Read request enters the PEX 8114 Prefetchable Memory space, with a TLP length and starting address such that all requested data is within a single Cache Line and is less than an entire Cache Line, a Memory Read request is issued on the PCI Bus. If a PCI Express Memory Read request enters PEX 8114 Prefetchable Memory space, with a TLP length greater than or equal to the Cache Line Size, but less than two Cache Lines in size, the PEX 8114 issues a Memory Read Line request on the PCI Bus.

When a PCI Express Memory Read request enters the PEX 8114’s Prefetchable Memory space, with a TLP length greater than or equal to two Cache Lines in size, the PEX 8114 issues a Memory Read Line Multiple request. Issuing of Memory Read Line Multiple requests can be disabled by clearing the Memory Read Line Multiple Enable bit. This method of determining whether to issue a Memory Read Line or Memory Read Line Multiple request applies only to PCI mode. In PCI-X mode, the Transaction Size is stated in the transaction and it is unnecessary to indicate the Transaction Size.

PCI Express-to-PCI Transaction Completion Size

Read Completions are arranged according to the following description. If the data quantity requested in the initial PCI Express Read request is less than or equal to the size of the maximum Read Completion Size, the data is returned to the PCI Express Requester in a single TLP. If the data quantity requested in the initial PCI Express Read request is more than the maximum Read Completion Size, or if the Read crosses a 4-KB Address Boundary space, the Completion is constructed into more than one TLP. The TLPs are sized at the maximum Read Completion Size, except for the final TLP, which is sized to complete the remainder of the transaction.

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PCI Express-to-PCI-X Transactions
In PCI-X mode, when a PCI Express device attempts a transaction from the PCI Express interface to the PCI-X Bus, the PEX 8114 translates the PCI Express transaction TLP into a PCI-X Burst transaction. In the most basic transaction, the PEX 8114 receives a TLP on the PCI Express lanes and translates the data into one or more PCI-X bursts. Credits for up to 6 KB of PCI Express Posted and Non-Posted transactions are issued. These transactions are queued according to the PCI Ordering Transaction rules in central memory, and transmitted to the PCI-X modules, as bandwidth allows.

PCI Express-to-PCI-X Posted Writes

For Posted Writes, typically including Memory Writes, no Completion information is returned to the PCI Express device that originated the transaction, and when the transaction is transmitted on the PCI-X Bus, the transaction is considered complete. If the PCI-X Bus is busy, the PEX 8114 can receive and retain many Posted PCI Express Write TLPs, limited only by the 6-KB central RAM’s capacity. These transactions are processed as quickly as possible, in the order received. Table 7-7 defines this process.

Table Posted Writes Initial PCI Express

Posted Transaction Type Memory Write

Message Request

Message Request with Payload

Resultant PCI Transaction

PCI Memory Write.

Interrupt messages cause changes on the PCI side of the bridge, which are translated to IntA to IntD. Internally, Power Management and error conditions can cause Error messages to generate to PCI Express side of the bridge.

Not supported

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PCI Express-to-PCI-X Non-Posted Transactions

PCI Express-to-PCI-X Non-Posted Transactions

In the case of Non-Posted PCI Express transactions which typically include Memory Reads and Configuration and I/O Writes and Reads , the PEX 8114 accepts the PCI Express TLP and creates and issues a PCI-X I/O or Configuration Write or Read request on the PCI-X Bus.

Non-Posted Writes

When the transaction is a Write, the PEX 8114 is prepared to transfer the entire burst as a single transaction on the PCI-X Bus.

Non-Posted Writes and Reads

When the Non-Posted PCI Express transaction is a Read request, the PEX 8114 issues a Read request on the PCI-X Bus, in an effort to fulfill the PCI Express Data request. The PCI-X Target of the request has the option of responding with a Split Completion or Immediate data the PEX 8114 accepts either response:
• If the PCI-X Target responds with a Split Response, the Target must complete the Split Response with a Split Completion, at least to the next ADB, at a later time.
• If the PCI-X device replies to the PCI-X Read request with Immediate data, the PCI-X Target must continue supplying Immediate data, up to the next ADB.

The PEX 8114 does not allow a device to respond with a single data disconnect, unless the device is prepared to respond with single data disconnects up to the next ADB or to the end of the transaction, whichever comes first. This requirement is supported by the PCI-X r1.0b and PCI-X r2.0a. After the PEX 8114 successfully transmits or receives all data, the PEX 8114 issues a Completion TLP to the PCI Express Requester.

Table 7-8 defines PCI Express Non-Posted requests and the resultant PCI transactions when the Non-Posted PCI Express request is received.

Table Non-Posted Writes and Reads

Initial PCI Express Non-Posted Transaction Type Memory Read Request Memory Read Locked I/O Write Request I/O Read Request Configuration Write Type 0 Configuration Read Type 0 Configuration Write Type 1 Configuration Read Type 1

Resultant PCI Transaction

PCI-X Memory Read or Memory Read Line Multiple Not supported returns a UR I/O Write I/O Read Configuration Write Type 0 Configuration Read Type 0 Configuration Write Type 1 or 0 Configuration Read Type 1 or 0

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Transaction Concurrency

The PEX 8114 supports up to eight Non-Posted PCI Express requests. Writes are serially processed on a first-come, first-served basis. Reads are attempted in parallel, that is, if one request receives a disconnect, the PEX 8114 attempts to gather data for another of the outstanding requests, moving from request to request in an effort to complete as many transactions as possible, as soon as possible.
If the Force Strong Ordering bit is a value of 0 and then set offset FA0h[8]=0, then 1 , after data is returned in response to a Read request, the PEX 8114 concentrates all requests on gathering data to complete that transaction until the transaction completes. If the Force Strong Ordering bit is already set and then set again, only one outstanding Read is allowed at a time.

All Posted and Non-Posted Write bursts on the PCI Bus can be no larger than the PCI Express Maximum Packet Size. There is no internal combining of Write TLPs in an effort to increase the PCI Burst Size. Read Completions are gathered from the PCI-X Bus as a single DWord Disconnect, Completions to the next ADB, or Completion of the entire requested data size. The Completion data is collected within the PEX 8114, then delivered to the PCI Express Requesters as TLP packets that are no larger than the Maximum Packet Size, until all data requested by the PCI Express device is satisfied.

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Transaction Transfer Failures

Transaction Transfer Failures

The previously described transactions are the set of legal and expected transactions. Successful Data transfer is dependent upon the PCI-X and PCI Express devices connected to the PEX 8114 performing, as described in the PCI r3.0, PCI-X r2.0a, and PCI Express r1.0a. When a device fails to correctly perform, the transaction is likely to fail. These failures typically result in transaction timeouts and the setting of internal register bits. The PCI Express-to-PCI/PCI-X Bridge r1.0 anticipates most of the typical failures and specifies error handling procedures for error condition recovery. The PEX 8114 supports these error handling routines, recovers internal resources, and logs errors according to the specifications. For further details on error handling and recovery, refer to Chapter 8, “Error Handling,” and the PCI Express-to-PCI/PCI-X Bridge r1.0.

The other side of this failure to flush a pending transaction from the bridge is that it is assumed that a transaction will not complete and quickly reclaim its internal buffers. To accommodate heavy traffic densities, the bridge has several selectable transaction timeout periods. These timeout periods are based upon PCI_CLK cycles and in PCI mode, can be selected as 210, 215, or 220 Clock cycles, or the timeout can be disabled. The following register bits are used to select these timeouts:
• Bridge Control register Primary Discard Timer bit offset 3Ch[24]
• Bridge Control register Secondary Discard Timer bit offset 3Ch[25] discussed further
in Section
• Disable Completion Timeout Timer offset FA0h[5] discussed further in Section
and Section
• Enable Long Completion Timeout Timer offset FA0h[6] discussed further in Section
and Section

Table 7-9 defines register bit Timer values as they apply to available timeouts.

When Completions are not returned to the PEX 8114, or when the endpoint does not accept returned Completions held within the PEX 8114, the bridge’s internal resources remain reserved to those uncompleted transactions and cannot be used for future transactions. The following sections describe how the PEX 8114 controls slow or stalled transactions:
• PCI Endpoint Fails to Retry Read Request
• PCI-X Endpoint Fails to Transmit Split Completion
• PCI-X Endpoint Allows Infinite Retries
• PCI Express Endpoint Fails to Return Completion Data

Table Clock Cycle Timeout Period Selection

Clock Cycle Timeout

Default 210 215 220

No Timer Disabled

Bridge Control Register

Primary Discard Timer Offset 3Ch[24]

Secondary Discard Timer

Offset 3Ch[25]

Note “X” indicates “Don’t Care.”

Disable Completion Timeout Timer Offset FA0h[5]

Enable Long Completion Timeout

Timer Offset FA0h[6]

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PCI Endpoint Fails to Retry Read Request

The Secondary Discard Timer monitors Completions located within the PEX 8114, waiting to return to the initial PCI Requester. This Timer applies in PCI mode, and only when the PCI device initiated the initial Read request. After the Completion returns from the PCI Express endpoint to the PEX 8114, if the original PCI Requester fails to Retry for the Read Completion, the data remains in the PEX 8114 and results in wasted resources.

The Timer times Completions within the PEX If a Completion is not requested by the initial PCI Requester before the Secondary Discard Timer times out, the Completion is dropped and the PEX 8114 reclaims the internal resources. The Timer can be configured by the Bridge Control register Secondary Discard Timer bit to time out at 210 PCI_CLK clock periods when set offset 3Ch[25]=1 , or 215 PCI_CLK clock periods when cleared offset 3Ch[25]=0 .

PCI-X Endpoint Fails to Transmit Split Completion

When the PEX 8114 receives and takes ownership of a PCI Express Read request, and successfully forwards that request to a PCI-X device and receives a Split Response, the PEX 8114 waits a specified length of time for a Split Completion from the PCI-X device. If that Split Completion fails to return within the specified time, the PEX 8114 reclaims its internal resources.

Table 7-10 defines the three available Timer settings, selectable by way of the Enable Long Completion Timeout Timer and Disable Completion Timeout Timer bits offset FA0h[6:5], respectively .

Table Timer Settings for Transmitting Split Completions
When the PEX 8114 attempts to master a PCI or PCI-X Read Request transaction onto the PCI-X Bus in response to a PCI Express endpoint Read request, it is expected that the PCI-X endpoint might not contain data that is immediately ready and can respond to the PEX 8114’s Read request with a Retry. In response to the Retry, the PEX 8114 re-attempts the Read request, and it is expected that a future Read attempt will be completed with data. If the endpoint infinitely replies to the PEX 8114 Read request with a Retry, the PEX 8114 terminates the transaction. To facilitate this, the number of Retries received for each Read request are counted. At which time, the PEX 8114 compares the value stored in the Maximum Read Cycle Value field offset FA0h[26:16] . If the number of Retries received matches the number stored in the Maximum Read Cycle Value field, the Read request is dropped and the Retry Failure Status bit is set offset FA0h[27]=1 . If the Force Strong Ordering bit is cleared offset FA0h[8]=0 , the PEX 8114 attempts up to eight Read requests in a Round-Robin scheme. A Retry Count for each of the eight Read requests is maintained, and compared, as it takes its turn at the PCI Bus.

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PCI Express Endpoint Fails to Return Completion Data

PCI Express Endpoint Fails to Return Completion Data

The PEX 8114 holds internal resources reserved to receive Completions. If the PCI Express endpoint responsible for a Completion fails to transmit a Completion, the PEX 8114’s internal resources are at risk of remaining reserved, waiting for a Completion that might never occur. The PEX 8114 contains an Internal Timer used to trigger the bridge to reclaim internal resources reserved for Completions that might never occur. Table 7-11 defines the three available Timer settings, selectable by way of the Enable Long Completion Timeout Timer and Disable Completion Timeout Timer bits offset FA0h[6:5], respectively .

When PCI Non-Posted requests and Completions from PCI Express-to-PCI are executed and no timeout is selected offset FA0h[6:5]=X1b , the buffer holding Completions for the PCI requests are not automatically reclaimed. However, after 220 clocks transpire without a Completion, the Completion Buffer Timeout status bit for that buffer offset F88h is set to indicate that the buffer is reserved for an extremely late Completion. When the timeout setting is set to 215 or 220 offset FA0h[6:5]=00b or 10b, respectively and the Completion fails to return before the timeout, the buffer is reclaimed after the timeout and reused. If after a transaction times out, and the buffer is scheduled for reuse, and the PCI endpoint Retries the Read request for the transaction that timed out, the PEX 8114 returns a Target Abort or FFFF_FFFFh, as selected by the Bridge Control register Master Abort Mode bit offset 3Ch[21] to indicate that a timeout occurred to the PCI endpoint. Each buffer can timeout and be reclaimed three times. After three reclaims and four timeouts, the Completion Buffer Timeout Status bit for that buffer is set, to indicate that the buffer can no longer be reclaimed. When a buffer times out, if a user or operating system confirms that no stale Completions are pending, the buffer can be re-initialized by writing 1 to the offset F88h bit representing that buffer.

There is a degree of risk involved in re-initializing buffers. If a stale Completion is pending, and the software is not aware of this, and the associated Completion Buffer Timeout Status bit is mistakenly cleared, the stale Completion can be mistaken for a Completion to a more-recent request, resulting in incorrect data being used for the Completion. If 32 PCI Read requests fail to complete by the PCI Express endpoint, all eight buffers timeout four times and all resources are consumed.

To prevent a lockup condition, the PEX 8114 automatically clears the Completion Buffer Timeout Status bits for all eight registers, allowing it to continue to accept Non-Posted requests. If a lockup condition occurs, the PEX 8114 can no longer accept Non-Posted PCI-X requests, which precludes Configuration Writes. It therefore becomes impossible to clear the buffer timeouts after all buffers time out.

Table Timer Settings for Receiving Completions

Offset FA0h[6:5] 00b 10b X1b

Timer Setting 215 PCI_CLK cycles timeout 220 PCI_CLK cycles timeout

No timeout

Note “X” indicates “Don’t Care.”

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Chapter 8 Error Handling

Forward Transparent Bridge Error Handling

For all errors detected by the bridge, the bridge sets the appropriate error status bit [both Conventional PCI/PCI-X Error bit s and PCI Express error status bit s ], and generates an Error message on the PCI Express interface, if enabled. Each error condition has an error severity level programmable by software, and a corresponding Error message generated on the PCI Express interface. Four bits control PCI Express interface Error message generation:
• PCI/PCI-X Command register SERR# Enable bit
• PCI Express Device Control register Correctable Error Reporting Enable bit
• PCI Express Device Control register Non-Fatal Error Reporting Enable bit
• PCI Express Device Control register Fatal Error Reporting Enable bit

ERR_COR messages are enabled for transmission if the Correctable Error Reporting Enable bit is set. ERR_NONFATAL messages are enabled for transmission if the SERR# Enable or Non-Fatal Error Reporting Enable bit is set. ERR_FATAL messages are enabled for transmission if the SERR# Enable or Fatal Error Reporting Enable bit is set. The Device Status register Correctable Error Detected, Non-Fatal Error Detected, and Fatal Error Detected status bits are set for the corresponding errors on the PCI Express interface, regardless of the Error Reporting Enable bit values.

Forward Transparent Bridge PCI Express Originating Interface Primary to Secondary

This section describes error support for transactions that cross the bridge if the originating side is the PCI Express interface, and the destination interface is operating in Conventional PCI/PCI-X modes. If a Write Request or Read Completion is received with a Poisoned TLP, consider the entire Data Payload of the PCI Express transaction as corrupt. Parity is inverted for all Data phases when completing the transaction on the PCI/PCI-X Bus. If a TLP is received and an ECRC error is detected, consider the entire TLP as corrupt and not forwarded, but dropped by the bridge.

Table 8-1 defines the translation a bridge must perform when forwarding a Non-Posted PCI Express request Write or Read to the PCI/PCI-X Bus, and the request is immediately completed on the PCI/ PCI-X Bus, normally or with an error condition.

Table Translation Bridge Action when Forwarding Non-Posted PCI Express Request to PCI/PCI-X Bus

Immediate PCI/PCI-X Termination Data Transfer with Parity error Non-Posted Writes Data Transfer with Parity error Reads Master Abort Target Abort

PCI Express Completion Status Unsupported Request Successful Poisoned TLP Unsupported Request Completer Abort

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Received Poisoned TLP

When the PCI Express interface receives a Write Request or Read Completion with poisoned data, the following occurs:

PCI Status register Detected Parity Error bit is set.

PCI Status register Master Data Parity Error bit is set if the Poisoned TLP is a Read Completion and the PCI Command register Parity Error Response Enable bit is set.
0 = Primary Discard Timer counts 215 PCI Clock cycles 1 = Primary Discard Timer counts 210 PCI Clock cycles
Secondary Discard Timer Pertains to the PCI Bus in Conventional PCI mode and Forward Transparent Bridge mode. Selects the number of PCI clocks the bridge waits for a Master on the secondary interface to repeat a Delayed Transaction request. The Counter starts after the Completion PCI Express Completion associated with the Delayed Transaction request reaches the head of the bridge’s downstream queue that is, all Ordering requirements are satisfied and the bridge is ready to complete the Delayed Transaction with the originating Master on the secondary bus . If the originating Master does not repeat the transaction before the Counter expires, the bridge deletes the Delayed Transaction from its queue and sets bit 26 Discard Timer Status .
0 = Secondary Discard Timer counts 215 PCI Clock cycles 1 = Secondary Discard Timer counts 210 PCI Clock cycles

Discard Timer Status Pertains to the PCI Bus in Conventional PCI mode. Set to 1 when bit 24 or 25 Primary Discard Timer or Secondary Discard Timer, respectively expires and a Delayed Completion is discarded from a queue in the PEX The default state of this bit after reset must be Once set, remains set until it is reset by writing 1 to this bit location.

Discard Timer SERR# Enable Pertains to the PCI Bus in Conventional PCI mode. When set to 1, enables the bridge to generate an ERR_FATAL or ERR_NONFATAL transaction when bit 25 Secondary Discard Timer expires and a Delayed Transaction is discarded from a queue in the PEX

Reserved

RO/Fwd RW/Rev

RW/Fwd RO/Rev

RWC RW

Serial EEPROM

No Yes

Yes No

Default

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Power Management Capability Registers

This section details the PEX 8114 Power Management Capability registers. Table 14-4 defines the register map.

Table Power Management Capability Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Power Management Capability

Next Capability Pointer 48h

Capability ID 01h

Data

Power Management Control/ Status Bridge Extensions

Power Management Status and Control

Register 40h Power Management Capability

Bit s
7:0 15:8 18:16 19 20 21 24:22
31:27

Capability ID Set to 01h, indicating that the data structure currently being pointed to is the PCI Power Management data structure.

Next Capability Pointer Default 48h points to the Message Signaled Interrupt Capability structure.

Version Default 011b indicates compliance with the PCI Power Mgmt. r1.2.

PME Clock Set to 1, as required by the PCI Express Base 1.0a.

Reserved

Device-Specific Initialization Default 0 indicates that Device-Specific Initialization is not required.

AUX Current Not supported Default 000b indicates that the PEX 8114 does not support Auxiliary Current requirements.

D1 Support Not supported Default 0 indicates that the PEX 8114 does not support the D1 Device PM state.

D2 Support Not supported Default 0 indicates that the PEX 8114 does not support the D2 Device PM state.

PME Support Default 1100_1b indicates that the PEX 8114 forwards PME messages in the D0, D3hot, and D3cold Device PM states.
PCI Express Relaxed Ordering Enabled 4 Not supported

Cleared to

Maximum Payload Size Power-on/reset value is 000b, indicating that initially the PEX 8114 is configured to support a Maximum Payload Size of 128 bytes. Software can change this field to configure the PEX 8114 to support Payload Sizes of 256 or Software must not change this field to values other than those indicated by the Device Capability register Maximum Payload Size Supported field offset 6Ch[2:0] . 7:5 000b = Indicates that initially, the PEX 8114 port is configured to support a Maximum Payload Size of 128 bytes 001b = Indicates that initially, the PEX 8114 port is configured to support a Maximum Payload Size of 256 bytes

No other encodings are supported.

Extended Tag Field Enable 8 Not supported

Cleared to

Phantom Functions Enable 9 Not supported

Cleared to

AUX Power PM Enable 10 Not supported

Cleared to

No Snoop Enable 11 Not supported

Cleared to

Type RW RO

Serial EEPROM

Default
000b

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Register 70h Device Status and Control Cont.

Bit s
14:12
15 16 17 18 19 20 21 31:22

Maximum Read Request Size Specifies the maximum size in bytes of a Read request generated by the PEX
000b = 128 bytes 001b = 256 bytes 010b = 512 bytes default 011b = 1,024 bytes 100b = 2,048 bytes 101b = 4,096 bytes 110b, 111b = Reserved

Bridge Configuration Retry Enable

Device Status

Correctable Error Detected Set when the PEX 8114 detects a Correctable error, regardless of the bit 0 Correctable Error Reporting Enabled state.
0 = PEX 8114 did not detect a Correctable error 1 = PEX 8114 detected a Correctable error

Non-Fatal Error Detected Set when the PEX 8114 detects a Non-Fatal error, regardless of the bit 1 Non-Fatal Error Reporting Enabled state.
0 = PEX 8114 did not detect a Non-Fatal error 1 = PEX 8114 detected a Non-Fatal error

Fatal Error Detected Set when the PEX 8114 detects a Fatal error, regardless of the bit 2 Fatal Error Reporting Enabled state.
0 = PEX 8114 did not detect a Fatal error 1 = PEX 8114 detected a Fatal error

Unsupported Request Detected Set when the PEX 8114 detects an Unsupported Request, regardless of the bit 3 Unsupported Request Reporting Enable state.
0 = PEX 8114 did not detect an Unsupported Request 1 = PEX 8114 detected an Unsupported Request

AUX Power Detected Not supported Cleared to

Transactions Pending 1 = Indicates that the bridge is waiting for a Completion from an outstanding transaction

Reserved

PCI Express Capability Registers

Type

Serial EEPROM
PCI Clock Enable, Strong Ordering, Read Cycle Value

Prefetch

Reserved

FA0h FA4h

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Register FA0h PCI Clock Enable, Strong Ordering, Read Cycle Value

Bit s

Type

Serial EEPROM

PCI_CLKO_EN[3:0] PCI_CLKO_EN[0]=1 enables PCI_CLKO0 3:0 PCI_CLKO_EN[1]=1 enables PCI_CLKO1 PCI_CLKO_EN[2]=1 enables PCI_CLKO2 PCI_CLKO_EN[3]=1 enables PCI_CLKO3

Cache Line Prefetch Line Count

Controls the number of lines prefetched during Memory Reads.
4 0 = 1 Cache Line
1 = 2 Cache Lines used only if the Miscellaneous Control register Cache Line Size field offset 0Ch[7:0] is less than or equal to 16 DWords 64 bytes

Disable Completion Timeout Timer 5 Refer to Section “Transaction Transfer Failures,”
for details.

Enable Long Completion Timeout Timer 6 Refer to Section “Transaction Transfer Failures,”
for details.
7 Disable BAR0
Force Strong Ordering

After data is returned to the PEX 8114 in response to a Read
8 request, the PEX 8114 Retries the same transaction until
complete and does not attempt to gather data from other
outstanding transactions.
9 Reserved

PLL Lock Control 0
10 Resets on loss of PLL lock, unless bits [11:10]=00b. Refer
to Table 14-25 for methods of handling loss of PLL lock.

PLL Lock Control 1 11 Reset after timer timeout on loss of PLL lock. Refer to

Table 14-25 for methods of handling loss of PLL lock.
12 Memory Read Line Multiple Enable
13 Address Stepping Enable
14 Sticky PCI-X PLL Loss Lock Set when the PCI-X PLL loses PLL lock.

RWCS
15 Sticky PCI Express PLL Loss Lock Set when the PCI Express PLL loses PLL lock.

RWCS
26:16 Maximum Read Cycle Value
27 Retry Failure Status
31:28 Reserved

Default
0h if STRAP_CLK_MST=0 Fh if STRAP_CLK_MST=1
0 7FFh 0 0h

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PCI-X-Specific Registers

Table Methods for Handling Loss of PLL Lock

Offset FA0h[11:10]

Default. Ignores loss of PLL lock.

A loss of PLL lock immediately causes the PEX 8114 to reset.

The PEX 8114 attempts to tolerate loss of PLL lock:
• When lock is re-acquired in less than 200 µs, the PEX 8114 does not reset
• When lock is not re-acquired within 200 µs, the PEX 8114 is reset

The PEX 8114 does not reset if loss of PLL lock occurs.

Register FA4h Prefetch

Bit s
7:0 Reserved

Prefetch Space Count

Valid only in PCI mode. Not used in PCI-X mode.

Specifies the number of DWords to prefetch for Memory Reads originating on the PCI Bus that are forwarded to the PCI Express interface. Only even values between 0 and 32 are allowed.
PCI Clock Enable, Strong Ordering, Read Cycle Value

FA4h

Prefetch

FA8h

Arbiter 0

FACh

Arbiter 1

FB0h

Arbiter 2

FB4h

Advanced Error Reporting Enhanced Capability Header

FB8h

Uncorrectable Error Status

FBCh

Uncorrectable Error Mask

FC0h

Uncorrectable Error Severity

FC4h

Correctable Error Status

FC8h

Correctable Error Mask

FCCh

Advanced Error Capabilities and Control

FD0h

Header Log_0

FD4h

Header Log_1

FD8h

Header Log_2

FDCh

Header Log_3

FE0h

Secondary Uncorrectable Error Status

FE4h

Secondary Uncorrectable Error Mask

FE8h

Secondary Uncorrectable Error Severity

FECh

Secondary Uncorrectable Error Pointer no serial EEPROM Write

FF0h

FF4h FF8h
Product Ordering Information
Contact your local PLX Sales Representative for ordering information.
Table C-1. Product Ordering Information

PEX8114-BC13BI PEX8114-BC13BI G

PEX8114-BD13BI PEX8114-BD13BI G

PEX 8114 PCI Express-to-PCI/PCI-X Bridge PBGA 17 x 17 mm2, 256-ball Package

PEX 8114 PCI Express-to-PCI/PCI-X Bridge PBGA 17 x 17 mm2, 256-ball Lead-Free RoHS Green Package

PEX 8114 PCI Express-to-PCI/PCI-X Bridge PBGA 17 x 17 mm2, 256-ball Package

PEX 8114 PCI Express-to-PCI/PCI-X Bridge PBGA 17 x 17 mm2, 256-ball Lead-Free RoHS Green Package

PEX8114-BD13 B I G

PEX 8114-BC RDK-F PEX 8114-BC RDK-R PEX 8114-BD RDK-F PEX 8114-BD RDK-R
8114 Part Number PEX PCI Express Product Family

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C.2 C.3

United States and International Representatives and Distributors

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Technical Support

PLX Technology, Inc., technical support information is listed at or call 800 759-3735 domestic only or 408

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Datasheet ID: PEX8114-BC13BI 520497