AT91FR4042-CI

AT91FR4042-CI Datasheet

• 256K Words 16-bit Flash Memory 4 Mbits Single Voltage Read/Write Sector Erase Architecture Low-power Operation Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection Reset Input for Device Initialization Factory-programmed AT91 Flash Uploader Software

Part	Datasheet
AT91FR4042-CI	AT91FR4042-CI (pdf)

Related Parts	Information
AT91FR4042-CI-T	AT91FR4042-CI-T

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• Incorporates the Processor Core High-performance 32-bit RISC Architecture High-density 16-bit Instruction Set Leader in MIPS/Watt Embedded ICE In-circuit Emulation • 256K Bytes of On-chip SRAM 2 Mbits 32-bit Data Bus, Single-clock Cycle Access • 256K Words 16-bit Flash Memory 4 Mbits Single Voltage Read/Write Sector Erase Architecture Low-power Operation Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection Reset Input for Device Initialization Factory-programmed AT91 Flash Uploader Software • Fully Programmable External Bus Interface EBI Up to Eight Chip Selects, Maximum External Address Space of 64M Bytes Software Programmable 8/16-bit External Data Bus • 8-level Priority, Individually Maskable, Vectored Interrupt Controller Four External Interrupts, Including a High-priority Low-latency Interrupt Request • 32 Programmable I/O Lines • 3-channel 16-bit Timer/Counter Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel • Two USARTs Two Dedicated Peripheral Data Controller PDC Channels per USART • Programmable Watchdog Timer • Advanced Power-saving Features CPU and Peripherals can be Deactivated Individually • Fully Static Operation: 0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.65V, 85°C • 2.7V to 3.6V I/O and Flash Operating Range, 1.65V to 1.95V Core Operating Range • -40°C to 85°C Temperature Range • Available in a 121-ball 10 x 10 x mm BGA Package with mm Ball Pitch AT91 Microcontrollers AT91FR4042 The AT91FR4042 is a member of the Atmel AT91 16/32-bit Microcontroller family, which is based on the ARM7TDMI processor core. The processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. The AT91FR4042 ARM microcontroller features 2 Mbits of on-chip SRAM and 4 Mbits of Flash memory in a single compact 121-ball BGA package. Its high level of integration and very small footprint make the device ideal for space-constrained applications. The high-speed on-chip SRAM enables a performance of up to 63 MIPs and significant power reduction over an external SRAM implementation. The Flash memory may be programmed via the JTAG/ICE interface or the factory-programmed Flash Uploader using a single device supply, making the AT91FR4042 suitable for in-system programmable applications. Pin Configuration Figure AT91FR4042 Pinout for 121-ball BGA Package Top View A1 Corner 10 11 P21/TXD1 NTRI P15 RXD0 P11 IRQ2 VDDCORE P8 TIOB2 P6 TCLK2 P2 TIOB0 P22 RXD1 P20 SCK1 P12 FIQ P10 IRQ1 VDDIO P7 TIOA2 P4 TIOA1 P1 TIOA0 VDDIO NUB NWR1 P14 TXD0 NBUSY P9 IRQ0 TIOB1 TCLK1 P0 TCLK0 Product overview Ordering information Packaging information Soldering profile Detailed description of Flash memory Document Title ARM7TDMI Thumb Datasheet AT91x40 Series Datasheet AT91R40008 Electrical Characteristics Datasheet AT49BV/LV4096A 4 megabit 256 K x 16/512 K x 8 Single Volt Flash Memory Datasheet AT91FR4042 Datasheet this document AT49BV/LV4096A 4 megabit 256 K x 16/512 K x 8 Single Volt Flash Memory Datasheet 8 AT91FR4042 AT91FR4042 Product Overview Power Supply Input/Output Considerations Master Clock Reset NRST Pin Watchdog Reset Emulation Functions Tri-state Mode The AT91FR4042 device has two types of power supply pins • VDDCORE pins that power the chip core i.e., the AT91R40008 with its embedded SRAM and peripherals • VDDIO pins that power the AT91R40008 I/O lines and the Flash memory An independent I/O supply allows a flexible adaptation to external component signal levels. The AT91FR4042 I/O pads accept voltage levels up to the VDDIO power supply limit. After the reset, the microcontroller peripheral I/Os are initialized as inputs to provide the user with maximum flexibility. It is recommended that in any application phase, the inputs to the microcontroller be held at valid logic levels to minimize the power consumption. The AT91FR4042 has a fully static design and works on the Master Clock MCK , provided on the MCKI pin from an external source. The Master Clock is also provided as an output of the device on the MCKO pin, which is multiplexed with a general purpose I/O line. While NRST is active, MCKO remains low After the reset, MCKO is valid and outputs an image of the MCK signal. The PIO Controller must be programmed to use this pin as standard I/O line. Reset restores the default states of the user interface registers defined in the user interface of each peripheral , and forces the ARM7TDMI to perform the next instruction fetch from address zero. Except for the program counter the ARM7TDMI registers do not have defined reset states. NRST is active low-level input. It is asserted asynchronously, but exit from reset is synchronized internally to the MCK. The signal presented on MCKI must be active within the specification for a minimum of 10 clock cycles up to the rising edge of NRST to ensure correct operation. The first processor fetch occurs 80 clock cycles after the rising edge of NRST. The watchdog can be programmed to generate an internal reset. In this case, the reset has the same effect as the NRST pin assertion, but the BMS and NTRI pins are not sampled. Boot Mode and Tri-state Mode are not updated. If the NRST pin is asserted and the watchdog triggers the internal reset, the NRST pin has priority. The AT91FR4042 microcontroller provides a tri-state mode, which is used for debug purposes. This enables the connection of an emulator probe to an application board without having to desolder the device from the target board. In tri-state mode, all the output pin drivers of the AT91R40008 microcontroller are disabled. In tri-state mode, direct access to the Flash via external pins is provided. This enables production Flash programming using classical Flash programmers prior to board mounting. JTAG/ICE Debug Memory Controller Internal Memories Boot Mode Select To enter tri-state mode, the NTRI pin must be held low during the last 10 clock cycles before the rising edge of NRST. For normal operation, the NTRI pin must be held high during reset by a resistor of up to 400 NTRI is multiplexed with I/O line P21 and USART1 serial data transmit line TXD1. ARM-standard embedded In-circuit Emulation is supported via the JTAG/ICE port. The TDI, TDO, TCK and TMS pins are dedicated to this debug function and can be connected to a host computer via the external ICE interface. In ICE Debug Mode, the ARM7TDMI core responds with a non-JTAG chip ID that identifies the microcontroller. This is not fully IEEE1149.1 compliant. The ARM7TDMI processor address space is 4G bytes. The memory controller decodes the internal 32-bit address bus and defines three address spaces • Internal memories in the four lowest megabytes • Middle space reserved for the external devices memory or peripherals controlled by the EBI • Internal peripherals in the four highest megabytes In any of these address spaces, the ARM7TDMI operates in little-endian mode only. The AT91FR4042 microcontroller integrates 256K bytes of internal SRAM. It is 32 bits wide and single-clock cycle accessible. Byte 8-bit , half-word 16-bit and word 32-bit accesses are supported and are executed within one cycle. Fetching either Thumb or ARM instructions is supported, and internal memory can store two times as many Thumb instructions as ARM instructions. The SRAM is mapped at address 0x0 after the Remap command , allowing ARM7TDMI exception vectors between 0x0 and 0x20 to be modified by the software. Placing the SRAM on-chip and using the 32-bit data bus bandwidth maximizes the microcontroller performance and minimizes system power consumption. The 32-bit bus increases the effectiveness of the use of the ARM instruction set and the processing of data that is wider than 16 bits, thus making optimal use of the ARM7TDMI advanced performance. Being able to dynamically update application software in the 256-Kbyte SRAM adds an extra dimension to the AT91FR4042. The AT91FR4042 also integrates a 4-Mbit Flash memory that is accessed via the External Bus Interface. All data, address and control lines, except for the Chip Select signal, are connected within the device. Ordering Information Table Ordering Information Ordering Code AT91FR4042-CI Package BGA 121 Temperature Operating Range Industrial -40°C to 85°C 18 AT91FR4042 Packaging Information Figure AT91FR4042 Package AT91FR4042 Table Thermal Resistance Data Parameter Condition Package Junction-to- 121-BGA ambient thermal Still Air resistance Junction-to-case thermal resistance 121-BGA Table Device and 121-ball BGA Package Maximum Weight Units °C/W Table 121-ball BGA Package Characterisicst Ball diameter Ball land Solder mask opening Plating material Solder ball material Moisture Sensitivity Level mm ± mm Copper Sn/Pb 3 20 AT91FR4042 Soldering Profile AT91FR4042 Table 8 gives the recommended soldering profile from J-STD-20. Table Soldering Profile Average Ramp-up Rate 183°C to Peak Preheat Temperature 125°C ±25°C Temperature Maintained Above 183°C Time within 5°C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25°C to Peak Temperature Convection or IR/Convection 3°C/sec. max. 120 sec. max 60 sec. to 150 sec. 10 sec. to 20 sec. 220 +5/-0°C or 235 +5/-0°C 6°C/sec. 6 min. max VPR 10°C/sec. 60 sec. 215 to 219°C or 235 +5/-0°C 10°C/sec. Small packages may be subject to higher temperatures if they are reflowed in boards with larger components. In this case, small packages may have to withstand temperatures of up to 235°C, not 220°C IR reflow . Recommended package reflow conditions depend on package thickness and volume. See Table Table Recommended Package Reflow Conditions 1, 2, 3 Parameter Convection VPR IR/Convection Temperature 220 +5/-0°C 215 to 219°C 220 +5/-0°C The packages are qualified by Atmel by using IR reflow conditions, not convection or VPR. By default, the package level 1 is qualified at 220°C unless 235°C is stipulated . The body temperature is the most important parameter but other profile parameters

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• Incorporates the Processor Core High-performance 32-bit RISC Architecture High-density 16-bit Instruction Set Leader in MIPS/Watt Embedded ICE In-circuit Emulation
• 256K Bytes of On-chip SRAM 2 Mbits 32-bit Data Bus, Single-clock Cycle Access
• 256K Words 16-bit Flash Memory 4 Mbits Single Voltage Read/Write Sector Erase Architecture Low-power Operation Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection Reset Input for Device Initialization Factory-programmed AT91 Flash Uploader Software
• Fully Programmable External Bus Interface EBI Up to Eight Chip Selects, Maximum External Address Space of 64M Bytes Software Programmable 8/16-bit External Data Bus
• 8-level Priority, Individually Maskable, Vectored Interrupt Controller Four External Interrupts, Including a High-priority Low-latency Interrupt Request
• 32 Programmable I/O Lines
• 3-channel 16-bit Timer/Counter

Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
• Two USARTs

Two Dedicated Peripheral Data Controller PDC Channels per USART
• Programmable Watchdog Timer
• Advanced Power-saving Features

CPU and Peripherals can be Deactivated Individually
• Fully Static Operation:
0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.65V, 85°C
• 2.7V to 3.6V I/O and Flash Operating Range, 1.65V to 1.95V Core Operating Range
• -40°C to 85°C Temperature Range
• Available in a 121-ball 10 x 10 x mm BGA Package with mm Ball Pitch

AT91 Microcontrollers

AT91FR4042

The AT91FR4042 is a member of the Atmel AT91 16/32-bit Microcontroller family, which is based on the ARM7TDMI processor core. The processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption.

The AT91FR4042 ARM microcontroller features 2 Mbits of on-chip SRAM and 4 Mbits of Flash memory in a single compact 121-ball BGA package. Its high level of integration and very small footprint make the device ideal for space-constrained applications. The high-speed on-chip SRAM enables a performance of up to 63 MIPs and significant power reduction over an external SRAM implementation.

The Flash memory may be programmed via the JTAG/ICE interface or the factory-programmed Flash Uploader using a single device supply, making the AT91FR4042 suitable for in-system programmable applications.

Pin Configuration

Figure AT91FR4042 Pinout for 121-ball BGA Package Top View

A1 Corner
10 11

P21/TXD1 NTRI

P15 RXD0

P11 IRQ2

VDDCORE

P8 TIOB2

P6 TCLK2

P2 TIOB0

P22 RXD1

P20 SCK1

P12 FIQ

P10 IRQ1

VDDIO

P7 TIOA2

P4 TIOA1

P1 TIOA0

VDDIO

NUB NWR1

P14 TXD0

NBUSY

P9 IRQ0

TIOB1 TCLK1

P0 TCLK0
Product overview Ordering information Packaging information Soldering profile

Detailed description of Flash memory

Document Title ARM7TDMI Thumb Datasheet

AT91x40 Series Datasheet AT91R40008 Electrical Characteristics Datasheet AT49BV/LV4096A 4 megabit 256 K x 16/512 K x 8 Single Volt Flash Memory Datasheet

AT91FR4042 Datasheet this document

AT49BV/LV4096A 4 megabit 256 K x 16/512 K x 8 Single Volt Flash Memory Datasheet
8 AT91FR4042

AT91FR4042

Product Overview

Power Supply

Input/Output Considerations Master Clock

Reset

NRST Pin

Watchdog Reset

Emulation Functions

Tri-state Mode

The AT91FR4042 device has two types of power supply pins
• VDDCORE pins that power the chip core i.e., the AT91R40008 with its embedded

SRAM and peripherals
• VDDIO pins that power the AT91R40008 I/O lines and the Flash memory An independent I/O supply allows a flexible adaptation to external component signal levels.

The AT91FR4042 I/O pads accept voltage levels up to the VDDIO power supply limit. After the reset, the microcontroller peripheral I/Os are initialized as inputs to provide the user with maximum flexibility. It is recommended that in any application phase, the inputs to the microcontroller be held at valid logic levels to minimize the power consumption.

The AT91FR4042 has a fully static design and works on the Master Clock MCK , provided on the MCKI pin from an external source.

The Master Clock is also provided as an output of the device on the MCKO pin, which is multiplexed with a general purpose I/O line. While NRST is active, MCKO remains low After the reset, MCKO is valid and outputs an image of the MCK signal. The PIO Controller must be programmed to use this pin as standard I/O line.

Reset restores the default states of the user interface registers defined in the user interface of each peripheral , and forces the ARM7TDMI to perform the next instruction fetch from address zero. Except for the program counter the ARM7TDMI registers do not have defined reset states.

NRST is active low-level input. It is asserted asynchronously, but exit from reset is synchronized internally to the MCK. The signal presented on MCKI must be active within the specification for a minimum of 10 clock cycles up to the rising edge of NRST to ensure correct operation. The first processor fetch occurs 80 clock cycles after the rising edge of NRST.

The watchdog can be programmed to generate an internal reset. In this case, the reset has the same effect as the NRST pin assertion, but the BMS and NTRI pins are not sampled. Boot Mode and Tri-state Mode are not updated. If the NRST pin is asserted and the watchdog triggers the internal reset, the NRST pin has priority.

The AT91FR4042 microcontroller provides a tri-state mode, which is used for debug purposes. This enables the connection of an emulator probe to an application board without having to desolder the device from the target board. In tri-state mode, all the output pin drivers of the AT91R40008 microcontroller are disabled.

In tri-state mode, direct access to the Flash via external pins is provided. This enables production Flash programming using classical Flash programmers prior to board mounting.

JTAG/ICE Debug

Memory Controller

Internal Memories

Boot Mode Select

To enter tri-state mode, the NTRI pin must be held low during the last 10 clock cycles before the rising edge of NRST. For normal operation, the NTRI pin must be held high during reset by a resistor of up to 400

NTRI is multiplexed with I/O line P21 and USART1 serial data transmit line TXD1.

ARM-standard embedded In-circuit Emulation is supported via the JTAG/ICE port. The TDI, TDO, TCK and TMS pins are dedicated to this debug function and can be connected to a host computer via the external ICE interface. In ICE Debug Mode, the ARM7TDMI core responds with a non-JTAG chip ID that identifies the microcontroller. This is not fully IEEE1149.1 compliant.

The ARM7TDMI processor address space is 4G bytes. The memory controller decodes the internal 32-bit address bus and defines three address spaces
• Internal memories in the four lowest megabytes
• Middle space reserved for the external devices memory or peripherals controlled
by the EBI
• Internal peripherals in the four highest megabytes

In any of these address spaces, the ARM7TDMI operates in little-endian mode only.

The AT91FR4042 microcontroller integrates 256K bytes of internal SRAM. It is 32 bits wide and single-clock cycle accessible. Byte 8-bit , half-word 16-bit and word 32-bit accesses are supported and are executed within one cycle. Fetching either Thumb or ARM instructions is supported, and internal memory can store two times as many Thumb instructions as ARM instructions.

The SRAM is mapped at address 0x0 after the Remap command , allowing ARM7TDMI exception vectors between 0x0 and 0x20 to be modified by the software.

Placing the SRAM on-chip and using the 32-bit data bus bandwidth maximizes the microcontroller performance and minimizes system power consumption. The 32-bit bus increases the effectiveness of the use of the ARM instruction set and the processing of data that is wider than 16 bits, thus making optimal use of the ARM7TDMI advanced performance.

Being able to dynamically update application software in the 256-Kbyte SRAM adds an extra dimension to the AT91FR4042.

The AT91FR4042 also integrates a 4-Mbit Flash memory that is accessed via the External Bus Interface. All data, address and control lines, except for the Chip Select signal, are connected within the device.
Ordering Information
Table Ordering Information
Ordering Code AT91FR4042-CI

Package BGA 121

Temperature Operating Range

Industrial -40°C to 85°C
18 AT91FR4042

Packaging Information

Figure AT91FR4042 Package

AT91FR4042

Table Thermal Resistance Data

Parameter

Condition

Package

Junction-to-
121-BGA
ambient thermal

Still Air
resistance

Junction-to-case thermal resistance
121-BGA

Table Device and 121-ball BGA Package Maximum Weight

Units °C/W

Table 121-ball BGA Package Characterisicst Ball diameter Ball land Solder mask opening Plating material Solder ball material Moisture Sensitivity Level
mm ± mm Copper Sn/Pb 3
20 AT91FR4042

Soldering Profile

AT91FR4042

Table 8 gives the recommended soldering profile from J-STD-20.

Table Soldering Profile

Average Ramp-up Rate 183°C to Peak Preheat Temperature 125°C ±25°C Temperature Maintained Above 183°C Time within 5°C of Actual Peak Temperature Peak Temperature Range

Ramp-down Rate Time 25°C to Peak Temperature

Convection or IR/Convection 3°C/sec. max. 120 sec. max 60 sec. to 150 sec. 10 sec. to 20 sec.
220 +5/-0°C or 235 +5/-0°C 6°C/sec. 6 min. max

VPR 10°C/sec.
60 sec. 215 to 219°C or 235 +5/-0°C 10°C/sec.

Small packages may be subject to higher temperatures if they are reflowed in boards with larger components. In this case, small packages may have to withstand temperatures of up to 235°C, not 220°C IR reflow .

Recommended package reflow conditions depend on package thickness and volume. See Table

Table Recommended Package Reflow Conditions 1, 2, 3

Parameter Convection VPR IR/Convection

Temperature 220 +5/-0°C 215 to 219°C 220 +5/-0°C

The packages are qualified by Atmel by using IR reflow conditions, not convection or VPR.

By default, the package level 1 is qualified at 220°C unless 235°C is stipulated . The body temperature is the most important parameter but other profile parameters

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Datasheet ID: AT91FR4042-CI 519117