ADP3163
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ADP3163JRUZ-REEL (pdf) |
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5-Bit Programmable 2-/3-Phase Synchronous Buck Controller ADP3163 FEATURES ADOPT Optimal Positioning Technology for Superior Load Transient Response and Fewest Output Capacitors Complies with VRM and Intel VR Down Guideline with Lowest System Cost Digitally Selectable 2- or 3-Phase Operation at up to 500 kHz per Phase Quad Logic-level PWM Outputs for Interface to External High-Power Drivers Active Current Balancing between All Output Phases Accurate Multiple VRM Module Current Sharing 5-Bit Digitally Programmable V to V Output Total Output Accuracy Over Temperature Current-Mode Operation Short Circuit Protection Enhanced Power Good Output Detects Open Outputs in Multi-VRM Power Systems Overvoltage Protection Crowbar Protects Microprocessors with No Additional External Components APPLICATIONS Desktop PC Power Supplies for: Intel 4 Processors AMD Athlon Processors VRM Modules REF GND FUNCTIONAL BLOCK DIAGRAM UVLO & BIAS 3.0V REFERENCE ADP3163 SET RESET CROWBAR 2-/3-PHASE DRIVER LOGIC DAC+20% OSCILLATOR SHARE COMP SOFT START POWER GOOD DAC+20% VID DAC PWM1 PWM2 PWM3 PGND PWRGD CS+ FB GENERAL DESCRIPTION The ADP3163 is a highly efficient multiphase synchronous buck switching regulator controller optimized for converting a 5 V or 12 V main supply into the core supply voltage required by high performance Intel processors. The ADP3163 uses an internal 5-bit DAC to read a voltage identification VID code directly from the processor, which is used to set the output voltage between V and V. The ADP3163 uses a current mode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VRM size and efficiency. The phase relationship of the output signals can be programmed to provide 2- or 3-phase operation, allowing for the construction of up to three complementary buck switching stages. These stages share the dc output current to reduce overall output voltage ripple. An active current balancing function ensures that all phases carry equal portions of the total load current, even under large transient loads, to minimize the size of the inductors. VID4 VID3 VID2 VID1 VID0 The ADP3163 also uses a unique supplemental regulation technique called active voltage positioning ADOPT to enhance load transient performance. Active voltage positioning results in a dc/dc converter that meets the stringent output voltage specifications for high performance processors, with the minimum number of output capacitors and smallest footprint. Unlike voltage-mode and standard current-mode architectures, active voltage positioning adjusts the output voltage as a function of the load current so that it is always optimally positioned for a system transient. The ADP3163 also provides accurate and reliable short circuit protection, adjustable current limiting, and an enhanced Power Good output that can detect open outputs in any phase for single or multi-VRM systems. The ADP3163 is specified over the commercial temperature range of 0°C to 70°C and is available in a 20-lead TSSOP package. ADOPT is a trademark of Analog Devices, Inc. Pentium is a registered trademark of Intel Corporation. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel 781/329-4700 Fax 781/326-8703 Analog Devices, Inc., 2001 VCC = 12 V, IREF = 150 TA = to unless otherwise noted. Parameter FEEDBACK INPUT Accuracy V Output V Output V Output Line Regulation Input Bias Current Crowbar Trip Point Crowbar Reset Point Crowbar Response Time REFERENCE Output Voltage Output Current VID INPUTS Input Low Voltage Input High Voltage Input Current Pull-Up Resistance Internal Pull-Up Voltage OSCILLATOR Maximum Frequency2 Frequency Variation CT Charge Current ORDERING GUIDE Package Description Thin Shrink Small Outline CAUTION ESD electrostatic discharge sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3163 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Package Option RU-20 TSSOP-20 WARNING! ESD SENSITIVE DEVICE ADP3163 Pin Name VID4 VID0 6 SHARE 7 COMP 8 GND 9 FB 10 CT 11 PWRGD 12 CS+ 13 14 PGND 15 PC 16 PWM3 17 PWM2 18 PWM1 19 REF 20 VCC PIN FUNCTION DESCRIPTIONS Function Voltage Identification DAC Inputs. These pins are pulled up to an internal 3 V reference, providing a Logic 1 if left open. The DAC output programs the FB regulation voltage from V to V. Leaving all five DAC inputs open results in the ADP3163 going into a “No CPU” mode, shutting off its PWM outputs. Current Sharing Output. This pin is connected to the SHARE pins of other ADP3163s in multiple VRM systems to ensure proper current sharing between the converters. The voltage at this output programs the output current control level between CS+ and Error Amplifier Output and Compensation Point. Ground. FB, REF and the VID DAC of the ADP3163 are referenced to this ground. This is a low current ground that can also be used as a return for the FB pin in remote voltage sensing applications. Feedback Input. Error amplifier input for remote sensing of the output voltage. External capacitor CT connection to ground sets the frequency of the device. Open drain output that signals when the output voltage is outside of the proper operating range or when a phase is not supplying current even if the output voltage is in specification. Current Sense Positive Node. Positive input for the current comparator. The output current is sensed as a voltage at this pin with respect to Current Sense Negative Node. Negative input for the current comparator. Power Ground. All internal biasing and logic output signals of the ADP3163 are referenced to this ground. Phase Control Input. This logic-level input determines the number of active phases and the duty cycle limit of each phase. Logic-Level Output for the Phase 3 Driver. Logic-Level Output for the Phase 2 Driver. Logic-Level Output for the Phase 1 Driver. V Reference Output. Supply Voltage for the ADP3163. ADP3163 5-BIT CODE 1 VID4 2 VID3 3 VID2 VCC 20 REF 19 100nF PWM1 18 4 VID1 PWM2 17 5 VID0 PWM3 16 6 SHARE PC 15 7 COMP PGND 14 100nF 8 GND 9 FB 10 CT 13 CS+ 12 PWRGD 11 Table I. PWM Outputs vs. Phase Control Code Maximum PWM3 PWM2 PWM1 Duty Cycle REF ON GND OFF AD820 |
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