ADG2108BCPZ-R2

ADG2108BCPZ-R2 Datasheet

ADG2108

Part	Datasheet
ADG2108BCPZ-R2	ADG2108BCPZ-R2 (pdf)

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Data Sheet CMOS 8 x 10 Unbuffered Analog Switch Array with Dual/Single Supplies ADG2108 I2C-compatible interface MHz high speed I2C option 32-lead LFCSP_WQ 5 mm x 5 mm Double-buffered input logic Simultaneous update of multiple switches Up to 300 MHz bandwidth Fully specified at dual ±5 V/single +12 V operation On resistance 35 maximum Low quiescent current < 20 µA AV switching in TV Automotive infotainment AV receivers CCTV Ultrasound applications KVM switching Telecom applications Test equipment/instrumentation PBX systems The ADG2108 is an analog cross point switch with an array size of 8 x The switch array is arranged so that there are eight columns by 10 rows, for a total of 80 switch channels. The array is bidirectional, and the rows and columns can be configured as either inputs or outputs. Each of the 80 switches can be addressed and configured through the I2Ccompatible interface. Standard, full speed, and high speed MHz I2C interfaces are supported. Any simultaneous switch combination is allowed. An additional feature of the ADG2108 is that switches can be updated simultaneously, using the LDSW command. In addition, a RESET option allows all of the switch channels to be reset/off. At power on, all switches are in the off condition. The device is packaged in a 32-lead, 5 mm x 5 mm LFCSP_WQ. ADG2108 FUNCTIONAL BLOCK DIAGRAM VDD VSS SCL SDA INPUT REGISTER 7 TO 80 DECODER 1 LATCHES LDSW LDSW 8 x 10 SWITCH ARRAY X0 TO X9 I/O 05898-001 A2 A1 A0 Y0 TO Y7 I/O Figure Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: Fax Analog Devices, Inc. All rights reserved. ADG2108* Product Page Quick Links Last Content Update 08/30/2016 Comparable Parts View a parametric search of comparable parts Evaluation Kits • ADG2108 Evaluation Board Documentation Data Sheet • ADG2108 CMOS 8 x 10 Unbuffered Analog Switch Array with Dual/Single Supplies Data Sheet User Guides • UG-465 Evaluation Board for the ADG2108 CMOS 8 x 10 Analog Switch Array with Dual/Single Supplies Reference Materials Product Selection Guide • High Speed Switches • Switches and Multiplexers Product Selection Guide Data Sheet Load Switch LDSW 18 Readback 18 Serial Interface 19 High Speed I2C Interface 19 Serial Bus Address 19 Writing to the ADG2108 20 Input Shift Register 20 Write 22 Read 22 Evaluation Board 24 Using the ADG2108 Evaluation Board 24 Power 24 Schematics 25 Outline Dimensions 27 Ordering Guide 27 Data Sheet ADG2108 SPECIFICATIONS VDD = 12 V ± 10%, VSS = 0 V, VL = 5 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted.1 Table Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Matching Between Channels, On Resistance Flatness, RFLAT ON LEAKAGE CURRENTS Channel Off Leakage, IOFF Channel On Leakage, ION DYNAMIC CHARACTERISTICS2 COFF CON tON tOFF THD + N PSRR −3 dB Bandwidth Off Isolation Channel-to-Channel Crosstalk Adjacent Channels Nonadjacent Channels Differential Gain Differential Phase Charge Injection LOGIC INPUTS Ax, RESET 2 Input High Voltage, VINH Input Low Voltage, VINL Input Leakage Current, IIN Input Capacitance, CIN B Version −40°C to +25°C +85°C VDD − 2 V 210 −69 −63 −76 ±1 7 Y Version −40°C to +25°C +125°C VDD − 2 V 210 −69 −63 −76 ±1 7 Unit Conditions V max typ max typ max typ max typ max typ max typ max µA typ µA typ VDD = V, VIN = 0 V, IS = −10 mA VDD = V, VIN = V, IS = −10 mA VDD = V, VIN = V, IS = −10 mA VDD = V, VIN = 0 V, IS = −10 mA VDD = V, VIN = 0 V to V, IS = −10 mA VDD = V, VIN = 0 V to V, IS = −10 mA VDD = V VX = 7 V/1 V, VY = 1 V/7 V VX = VY = 1 V or 7 V pF typ pF typ ns typ ns max ns typ ns max % typ dB typ MHz typ MHz typ dB typ dB typ dB typ % typ ° typ pC typ In addition to standard and full speed I2C, the ADG2108 also supports the high speed MHz I2C interface. Only the -HS models provide this added performance. See the Ordering Guide for details. SERIAL BUS ADDRESS The ADG2108 has a 7-bit slave address. The four MSBs are hard coded to 1110, and the three LSBs are determined by the state of Pin A0, Pin A1, and Pin A2. By offering the facility to hardware configure Pin A0, Pin A1, and Pin A2, up to eight of these devices can be connected to a single serial bus. The 2-wire serial bus protocol operates as follows: The master initiates data transfer by establishing a start condition, defined as when a high-to-low transition on the SDA line occurs while SCL is high. This indicates that an address/data stream follows. All slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address MSB first plus an R/W bit that determines the direction of the data transfer, that is, whether data is written to or read from the slave device. ADG2108 The peripheral whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse, known as the acknowledge bit. At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/W bit is 1 high , the master reads from the slave device. If the R/W bit is 0 low , the master writes to the slave device. Data is transmitted over the serial bus in sequences of nine clock pulses eight data bits followed by an acknowledge bit from the receiver of the data. Transitions on the SDA line must occur during the low period of the clock signal, SCL, and remain stable during the high period of SCL because a low-to-high transition when the clock is high can be interpreted as a stop signal. When all data bits have been read or written, a stop condition is established by the master. A stop condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the ninth clock pulse that is, the SDA line remains high . The master then brings the SDA line low before the 10th clock pulse and then high during the 10th clock pulse to establish a stop condition. Refer to Figure 33 and Figure 34 for a graphical explanation of the serial data transfer protocol. ADG2108 Data Sheet WRITING TO THE ADG2108 INPUT SHIFT REGISTER The input shift register is 24 bits wide. A 3-byte write is necessary when writing to this register and is done under the control of the serial clock input, SCL. The contents of the three bytes of the input shift register are shown in Figure 33 and described in Table DB23 MSB 111 DB16 LSB 0 A2 A1 A0 R/W DB15 MSB DB8 LSB DATA AX3 AX2 AX1 AX0 AY2 AY1 AY0 DB7 MSB DB0 LSB X LDSW 05898-004 DEVICE ADDRESS DATA BITS Figure Data-Words DATA BITS Table Input Shift Register Bit Function Descriptions Mnemonic Descriptions DB23 to DB17 1110xxx The MSBs of the ADG2108 are set to The LSBs of the address byte are set by the state of the three address pins, Pin A0, Pin A1, and Pin A2. DB16 Controls whether the ADG2108 slave device is read from or written to. If R/W = 1, the ADG2108 is being read from. If R/W = 0, the ADG2108 is being written to. DB15 Data Controls whether the switch is to be opened off or closed on . If Data = 0, the switch is opened/off. ORDERING GUIDE Model1 ADG2108BCPZ-REEL7 ADG2108BCPZ-HS-RL7 ADG2108YCPZ-REEL7 ADG2108YCPZ-HS-RL7 EVAL-ADG2108EBZ Temperature Range to +85°C to +85°C to +125°C to +125°C 1 Z = RoHS Compliant Part. 2 Formerly CP-32-2 package. I2C Speed 100 kHz, 400 kHz 100 kHz, 400 kHz, MHz 100 kHz, 400 kHz 100 kHz, 400 kHz, MHz Package Description 32-Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Frame Chip Scale Package [LFCSP_WQ] 10 x 8 Evaluation Board Package Option2 CP-32-7 CP-32-7 CP-32-7 CP-32-7 ADG2108 NOTES Data Sheet Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05898-0-9/12 B

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Data Sheet

CMOS 8 x 10 Unbuffered Analog Switch Array with Dual/Single Supplies

ADG2108

I2C-compatible interface MHz high speed I2C option
32-lead LFCSP_WQ 5 mm x 5 mm Double-buffered input logic

Simultaneous update of multiple switches Up to 300 MHz bandwidth Fully specified at dual ±5 V/single +12 V operation On resistance 35 maximum Low quiescent current < 20 µA

AV switching in TV Automotive infotainment AV receivers CCTV Ultrasound applications KVM switching Telecom applications Test equipment/instrumentation PBX systems

The ADG2108 is an analog cross point switch with an array size of 8 x The switch array is arranged so that there are eight columns by 10 rows, for a total of 80 switch channels. The array is bidirectional, and the rows and columns can be configured as either inputs or outputs. Each of the 80 switches can be addressed and configured through the I2Ccompatible interface. Standard, full speed, and high speed MHz I2C interfaces are supported. Any simultaneous switch combination is allowed. An additional feature of the ADG2108 is that switches can be updated simultaneously, using the LDSW command. In addition, a RESET option allows all of the switch channels to be reset/off. At power on, all switches are in the off condition. The device is packaged in a 32-lead, 5 mm x 5 mm LFCSP_WQ.

ADG2108

FUNCTIONAL BLOCK DIAGRAM

VDD VSS

SCL SDA

INPUT

REGISTER
7 TO 80

DECODER
1 LATCHES

LDSW

LDSW
8 x 10 SWITCH ARRAY

X0 TO X9 I/O
05898-001

A2 A1 A0

Y0 TO Y7 I/O

Figure

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel:

Fax Analog Devices, Inc. All rights reserved.

ADG2108* Product Page Quick Links

Last Content Update 08/30/2016

Comparable Parts

View a parametric search of comparable parts

Evaluation Kits
• ADG2108 Evaluation Board

Documentation

Data Sheet
• ADG2108 CMOS 8 x 10 Unbuffered Analog Switch

Array with Dual/Single Supplies Data Sheet User Guides
• UG-465 Evaluation Board for the ADG2108 CMOS
8 x 10 Analog Switch Array with Dual/Single Supplies

Reference Materials

Product Selection Guide
• High Speed Switches
• Switches and Multiplexers Product Selection Guide
Data Sheet
Load Switch LDSW 18 Readback 18 Serial Interface 19 High Speed I2C Interface 19 Serial Bus Address 19 Writing to the ADG2108 20 Input Shift Register 20 Write 22 Read 22 Evaluation Board 24 Using the ADG2108 Evaluation Board 24 Power 24 Schematics 25 Outline Dimensions 27 Ordering Guide 27

Data Sheet

ADG2108

SPECIFICATIONS

VDD = 12 V ± 10%, VSS = 0 V, VL = 5 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted.1

Table

Parameter ANALOG SWITCH

Analog Signal Range On Resistance, RON

On Resistance Matching Between Channels,

On Resistance Flatness, RFLAT ON

LEAKAGE CURRENTS Channel Off Leakage, IOFF Channel On Leakage, ION

DYNAMIC CHARACTERISTICS2 COFF CON tON
tOFF

THD + N

PSRR
−3 dB Bandwidth

Off Isolation Channel-to-Channel Crosstalk

Adjacent Channels Nonadjacent Channels Differential Gain Differential Phase Charge Injection LOGIC INPUTS Ax, RESET 2 Input High Voltage, VINH Input Low Voltage, VINL Input Leakage Current, IIN

Input Capacitance, CIN

B Version
−40°C to +25°C +85°C

VDD − 2 V
210 −69
−63 −76
±1 7

Y Version
−40°C to +25°C +125°C

VDD − 2 V
210 −69
−63 −76
±1 7

Unit

Conditions

V max typ max typ max typ max typ max typ max typ max
µA typ µA typ

VDD = V, VIN = 0 V, IS = −10 mA VDD = V, VIN = V, IS = −10 mA VDD = V, VIN = V, IS = −10 mA VDD = V, VIN = 0 V, IS = −10 mA VDD = V, VIN = 0 V to V, IS = −10 mA VDD = V, VIN = 0 V to V, IS = −10 mA

VDD = V VX = 7 V/1 V, VY = 1 V/7 V VX = VY = 1 V or 7 V
pF typ pF typ ns typ ns max ns typ ns max % typ
dB typ

MHz typ MHz typ dB typ
dB typ dB typ % typ ° typ pC typ
In addition to standard and full speed I2C, the ADG2108 also supports the high speed MHz I2C interface. Only the -HS models provide this added performance. See the Ordering Guide for details.

SERIAL BUS ADDRESS

The ADG2108 has a 7-bit slave address. The four MSBs are hard coded to 1110, and the three LSBs are determined by the state of Pin A0, Pin A1, and Pin A2. By offering the facility to hardware configure Pin A0, Pin A1, and Pin A2, up to eight of these devices can be connected to a single serial bus.

The 2-wire serial bus protocol operates as follows:

The master initiates data transfer by establishing a start condition, defined as when a high-to-low transition on the SDA line occurs while SCL is high. This indicates that an address/data stream follows. All slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address MSB first plus an R/W bit that determines the direction of the data transfer, that is, whether data is written to or read from the slave device.

ADG2108

The peripheral whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse, known as the acknowledge bit. At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/W bit is 1 high , the master reads from the slave device. If the R/W bit is 0 low , the master writes to the slave device.

Data is transmitted over the serial bus in sequences of nine clock pulses eight data bits followed by an acknowledge bit from the receiver of the data. Transitions on the SDA line must occur during the low period of the clock signal, SCL, and remain stable during the high period of SCL because a low-to-high transition when the clock is high can be interpreted as a stop signal.

When all data bits have been read or written, a stop condition is established by the master. A stop condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the ninth clock pulse that is, the SDA line remains high . The master then brings the SDA line low before the 10th clock pulse and then high during the 10th clock pulse to establish a stop condition.

Refer to Figure 33 and Figure 34 for a graphical explanation of the serial data transfer protocol.

ADG2108

Data Sheet

WRITING TO THE ADG2108

INPUT SHIFT REGISTER

The input shift register is 24 bits wide. A 3-byte write is necessary when writing to this register and is done under the control of the serial clock input, SCL. The contents of the three bytes of the input shift register are shown in Figure 33 and described in Table

DB23 MSB 111

DB16 LSB 0 A2 A1 A0 R/W

DB15 MSB

DB8 LSB

DATA AX3 AX2 AX1 AX0 AY2 AY1 AY0

DB7 MSB

DB0 LSB

X LDSW
05898-004

DEVICE ADDRESS

DATA BITS

Figure Data-Words

DATA BITS

Table Input Shift Register Bit Function Descriptions

Mnemonic

Descriptions

DB23 to DB17
1110xxx

The MSBs of the ADG2108 are set to The LSBs of the address byte are set by the state of the three address pins, Pin A0, Pin A1, and Pin A2.

DB16

Controls whether the ADG2108 slave device is read from or written to.

If R/W = 1, the ADG2108 is being read from.

If R/W = 0, the ADG2108 is being written to.

DB15

Data

Controls whether the switch is to be opened off or closed on . If Data = 0, the switch is opened/off.
ORDERING GUIDE

Model1 ADG2108BCPZ-REEL7 ADG2108BCPZ-HS-RL7 ADG2108YCPZ-REEL7 ADG2108YCPZ-HS-RL7 EVAL-ADG2108EBZ

Temperature Range to +85°C to +85°C to +125°C to +125°C
1 Z = RoHS Compliant Part. 2 Formerly CP-32-2 package.

I2C Speed 100 kHz, 400 kHz 100 kHz, 400 kHz, MHz 100 kHz, 400 kHz 100 kHz, 400 kHz, MHz

Package Description 32-Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Frame Chip Scale Package [LFCSP_WQ] 10 x 8 Evaluation Board

Package Option2

CP-32-7 CP-32-7 CP-32-7 CP-32-7

ADG2108 NOTES

Data Sheet

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

D05898-0-9/12 B

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Datasheet ID: ADG2108BCPZ-R2 517810