AD-FMCJESDADC1-EBZ

AD-FMCJESDADC1-EBZ Datasheet

ADI AD-FMCJESDADC1-EBZ Boards & Xilinx Reference Design

Part	Datasheet
AD-FMCJESDADC1-EBZ	AD-FMCJESDADC1-EBZ (pdf)

PDF Datasheet Preview
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • Tel • Fax • ADI AD-FMCJESDADC1-EBZ Boards & Xilinx Reference Design Introduction The AD-FMCJESDADC1-EBZ is a high speed data acquisition 4 ADC channels at 250MSPS , in an FMC form factor, which has two high speed JESD-204B Analog to Digital converters AD9250 on it. This board is similar to the 4DSP FMC-176, which in addition to the AD9250, has two AD9129 DACs. This reference design works for either of the boards, for details see fmc-176_information section. Also included in this wiki is a dual AD-FMCJESDADC1-EBZ on VC707 reference design, for details see Dual AD-FMCJESDADC1-EBZ section. The AD9250 is a dual, 14-bit ADC with sampling speeds of up to 250 MSPS. It features a multistage, differential pipelined architecture with integrated output error correction logic. It supports wide bandwidth inputs for a variety of user-selectable input ranges. The AD9250 features JESD204B high speed serial interface. The boards also feature the AD9517-1 for multi-output clock distribution with sub-picosecond jitter performance, along with an on-chip PLL and VCO. The devices may be clocked by either an internal clock source optionally locked to an external reference or an externally supplied sample clock. It also features an external trigger input for customized sampling control. The card is mechanically and electrically compliant to the FMC standard ANSI/VITA The reference design includes the device data capture via the JESD204B serial interface and the SPI interface. The samples are written to the external DDR-DRAM. It allows programming the device and monitoring it's internal registers via SPI. Supported Devices q AD-FMCJESDADC1-EBZ ADI Supported Carriers q ML605 q KC705 q VC707 q ZC706 Quick Start Guide The reference design zip file contains a bit file combined with a SDK elf file for a quick demonstration of the programming, RF conversion and data capture. All you need is the hardware and a PC running a UART terminal and the programmer IMPACT . Required Hardware q ML605, KC705 or VC707 board q AD-FMCJESDADC1-EBZ q Signal generators for ADC inputs Required Software q Xilinx ISE Programmer IMPACT is sufficient for the demo and is available on Webpack . q A UART terminal Tera Term/Hyperterminal , Baud rate Bit file q Download the gzip file and extract the sw/cf_fmc176_kc705.bit file. Running Demo SDK Program To begin make the following connections see image below q Connect the AD-FMCJESDADC1-EBZ board to the FMC-HPC connector of ML605/KC705 FMC1-HPC if VC707 board. q Connect power to ML605/KC705/VC707. q Connect two USB cables from the PC to the JTAG and UART USB connectors on ML605/KC705/VC707. q Connect signal generators to the A3, A2, A1 and/or A0 connectors. The quick start bit file configures the AD9517 to generate 250MHz clock to AD9250. It runs both the ADCs through all test modes and verifies the captured data accordingly. After the hardware setup, turn the power on.. Start IMPACT, and initialze the JTAG chain. The program should recognize the 7 series device. Start a UART terminal set to 57600 baud rate and then program the device. If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. After programming the devices, the program checks data capture on various test modes. After patterns and prbs sequences are verified, if no errors are present, you may use the chipscope busplot to see the captured signal see below . A chipscope project file is available inside the sw directory. Using the reference design The reference design is built on a microblaze based system parameterized for linux. A functional block diagram of the design is given below. The reference design contains both ADC and DAC pcores. If you are using the AD-FMCJESDADC1-EBZ, you can ignore the DAC pcores. The reference design consists of two identical instances of pcores for the DAC. On the ADC side, it consists of a single JESD core using Xilinx IP and two identical instances of AD9250 pcores. The AD9129 core consists of three functional modules, the DAC interface, a DDS using Xilinx IP and a VDMA interface. The frequency of DDS may be set via the programming interface. Alternatively a custom data sequence may be used via the VDMA interface. The AD9250 core consists of three functional modules, the ADC interface, a PN9/PN23 monitor and a DMA interface. The ADC interface captures and buffers data from the JESD core. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture overflow, over the range are reported back to the software. All the pcores have an AXI lite interface that allows control and monitoring of data generation and/or capture. The reference design also includes HDMI cores for GTX eye scan. Registers Please refer to the regmap.txt file in the pcores directory. Changing ADC Sample Rates The ADC sampling rate can vary from 40MHz to 250MHz. However, there are limitations imposed by the FPGA that may lower this range. In some cases, you may have to regenerate the cores for a different range. The reference design uses GTX channel PLL primitives and Xilinx's JESD core IP. The default design runs at 250MHz clock 5Gbps rate . As of this writing, the GTX specification & switching characteristics may be found at: The key switching characteristics are- The reference clock has a range of 60MHz to 670MHz 700MHz . This limits the minimum sampling clock to 60MHz. Though it is NOT recommended, it is possible to use AD9517 to generate a 40MHz sampling clock to AD9250 and a 80MHz reference clock to the FPGA. The line rate however, varies based on speed grade, package type and the use of CPLL vs QPLL. The CPLL supports rates between 0.5Gbps to 6.6Gbps the core may have to be changed for rates less than 3.2Gbps sampling rate 160MHz - and the IP may not support all the combinations . Again, it is possible to run the device on a single lane at a higher rate rather than 2 lanes each at a lower rate to circumvent some of the troubles of line rate dependency on parametrization, package type and speed grade. You must carefully evaluate these specifications against your requirements to run the design at a specific sampling frequency or a range . As always, if you have any questions or run into any problems, ask help & support. JESD Interface The default chipscope also captures the GTX/JESD core interface for a quick check on the transfer phases. There is a simple state machine within the pcore that walks through all the phases of the JESD specification. A sample screenshot is given below. The default signals are: The following signals are per lane GTX . Refer to Xilinx documentation on details of these signals. rx_data

PDF Datasheet Preview

One Technology Way
• P.O. Box 9106
• Norwood, MA 02062-9106
• Tel
• Fax
•

ADI AD-FMCJESDADC1-EBZ Boards & Xilinx Reference Design

Introduction

The AD-FMCJESDADC1-EBZ is a high speed data acquisition 4 ADC channels at 250MSPS , in an FMC form factor, which has two high speed JESD-204B Analog to Digital converters AD9250 on it.

This board is similar to the 4DSP FMC-176, which in addition to the AD9250, has two AD9129 DACs. This reference design works for either of the boards, for details see fmc-176_information section.

Also included in this wiki is a dual AD-FMCJESDADC1-EBZ on VC707 reference design, for details see Dual AD-FMCJESDADC1-EBZ section. The AD9250 is a dual, 14-bit ADC with sampling speeds of up to 250 MSPS. It features a multistage, differential pipelined architecture with integrated output error correction logic. It supports wide bandwidth inputs for a variety of user-selectable input ranges. The AD9250 features JESD204B high speed serial interface. The boards also feature the AD9517-1 for multi-output clock distribution with sub-picosecond jitter performance, along with an on-chip PLL and VCO. The devices may be clocked by either an internal clock source optionally locked to an external reference or an externally supplied sample clock. It also features an external trigger input for customized sampling control. The card is mechanically and electrically compliant to the FMC standard ANSI/VITA The reference design includes the device data capture via the JESD204B serial interface and the SPI interface. The samples are written to the external DDR-DRAM. It allows programming the device and monitoring it's internal registers via SPI.

Supported Devices
q AD-FMCJESDADC1-EBZ ADI

Supported Carriers
q ML605 q KC705 q VC707 q ZC706

Quick Start Guide

The reference design zip file contains a bit file combined with a SDK elf file for a quick demonstration of the programming, RF conversion and data capture. All you need is the hardware and a PC running a UART terminal and the programmer IMPACT .

Required Hardware
q ML605, KC705 or VC707 board q AD-FMCJESDADC1-EBZ q Signal generators for ADC inputs

Required Software
q Xilinx ISE Programmer IMPACT is sufficient for the demo and is available on Webpack . q A UART terminal Tera Term/Hyperterminal , Baud rate

Bit file
q Download the gzip file and extract the sw/cf_fmc176_kc705.bit file.

Running Demo SDK Program

To begin make the following connections see image below q Connect the AD-FMCJESDADC1-EBZ board to the FMC-HPC connector of ML605/KC705 FMC1-HPC if

VC707 board. q Connect power to ML605/KC705/VC707. q Connect two USB cables from the PC to the JTAG and UART USB connectors on ML605/KC705/VC707. q Connect signal generators to the A3, A2, A1 and/or A0 connectors.

The quick start bit file configures the AD9517 to generate 250MHz clock to AD9250. It runs both the ADCs through all test modes and verifies the captured data accordingly. After the hardware setup, turn the power on..

Start IMPACT, and initialze the JTAG chain. The program should recognize the 7 series device. Start a UART terminal set to 57600 baud rate and then program the device. If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. After programming the devices, the program checks data capture on various test modes.

After patterns and prbs sequences are verified, if no errors are present, you may use the chipscope busplot to see the captured signal see below . A chipscope project file is available inside the sw directory.

Using the reference design

The reference design is built on a microblaze based system parameterized for linux. A functional block diagram of the design is given below. The reference design contains both ADC and DAC pcores. If you are using the AD-FMCJESDADC1-EBZ, you can ignore the DAC pcores.

The reference design consists of two identical instances of pcores for the DAC. On the ADC side, it consists of a single JESD core using Xilinx IP and two identical instances of AD9250 pcores. The AD9129 core consists of three functional modules, the DAC interface, a DDS using Xilinx IP and a VDMA interface. The frequency of DDS may be set via the programming interface. Alternatively a custom data sequence may be used via the VDMA interface. The AD9250 core consists of three functional modules, the ADC interface, a PN9/PN23 monitor and a DMA interface. The ADC interface captures and buffers data from the JESD core. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture overflow, over the range are reported back to the software. All the pcores have an AXI lite interface that allows control and monitoring of data generation and/or capture. The reference design also includes HDMI cores for GTX eye scan.

Registers

Please refer to the regmap.txt file in the pcores directory.

Changing ADC Sample Rates

The ADC sampling rate can vary from 40MHz to 250MHz. However, there are limitations imposed by the FPGA that may lower this range. In some cases, you may have to regenerate the cores for a different range. The reference design uses GTX channel PLL primitives and Xilinx's JESD core IP. The default design runs at 250MHz clock 5Gbps rate .

As of this writing, the GTX specification & switching characteristics may be found at:

The key switching characteristics are-

The reference clock has a range of 60MHz to 670MHz 700MHz . This limits the minimum sampling clock to 60MHz. Though it is NOT recommended, it is possible to use AD9517 to generate a 40MHz sampling clock to AD9250 and a 80MHz reference clock to the FPGA.

The line rate however, varies based on speed grade, package type and the use of CPLL vs QPLL. The CPLL supports rates between 0.5Gbps to 6.6Gbps the core may have to be changed for rates less than 3.2Gbps sampling rate 160MHz - and the IP may not support all the combinations . Again, it is possible to run the device on a single lane at a higher rate rather than 2 lanes each at a lower rate to circumvent some of the troubles of line rate dependency on parametrization, package type and speed grade.

You must carefully evaluate these specifications against your requirements to run the design at a specific sampling frequency or a range . As always, if you have any questions or run into any problems, ask help & support.

JESD Interface

The default chipscope also captures the GTX/JESD core interface for a quick check on the transfer phases. There is a simple state machine within the pcore that walks through all the phases of the JESD specification. A sample screenshot is given below.

The default signals are:

The following signals are per lane GTX . Refer to Xilinx documentation on details of these signals.
rx_data

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived AD-FMCJESDADC1-EBZ Datasheet file may be downloaded here without warranties.

Datasheet ID: AD-FMCJESDADC1-EBZ 517689