74ALVC162839TX

74ALVC162839TX Datasheet

74ALVC162839 Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs/Outputs and Series Resistors in the Outputs

Part	Datasheet
74ALVC162839TX	74ALVC162839TX (pdf)

Related Parts	Information
74ALVC162839T	74ALVC162839T

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74ALVC162839 Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs/Outputs and Series Resistors in the Outputs 74ALVC162839 Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs/Outputs and Series Resistors in the Outputs The ALVC162839 contains twenty non-inverting selectable buffered or registered paths. The device can be configured to operate in a registered, or flow through buffer mode by utilizing the register enable REGE and Clock CLK signals. The device operates in a 20-bit word wide mode. All outputs can be placed into 3-STATE through use of the OE pin. These devices are ideally suited for buffered or registered 168 pin and 200 pin SDRAM DIMM memory modules. The 74ALVC162839 is designed for low voltage 1.65V to 3.6V VCC applications with I/O compatibility up to 3.6V. The 74ALVC162839 is also designed with series resistors in the outputs. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. The 74ALVC162839 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. s Compatible with PC100 and PC133 DIMM module specifications s VCC supply operation s 3.6V tolerant inputs and outputs s series resistors in the outputs s tPD CLK to On ns max for 3.0V to 3.6V VCC ns max for 2.3V to 2.7V VCC ns max for 1.65V to 1.95V VCC s Power-off high impedance inputs and outputs s Supports live insertion and withdrawal Note 1 s Uses patented noise/EMI reduction circuitry s Latchup conforms to JEDEC JED78 s ESD performance Human body model > 2000V Machine model > 200V Note 1 To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74ALVC162839T MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names OE CLK REGE Description Output Enable Input Active LOW Inputs Outputs Clock Input Register Enable Input 2001 Fairchild Semiconductor Corporation DS500712 74ALVC162839 Connection Diagram Logic Diagram Truth Table Inputs Outputs REGE H = Logic HIGH L = Logic LOW X = Don’t Care, but not floating Z = High Impedance = LOW-to-HIGH Clock Transition Functional Description The 74ALVC162839 consists of twenty selectable noninverting buffers or registers with word wide modes. Mode functionality is selected through operation of the CLK and REGE pin as shown by the truth table. When REGE is held at a logic HIGH the device operates as a 20-bit register. Data is transferred from In to On the rising edge of the CLK input. When the REGE pin is held at a logic LOW the device operates in a flow through mode and data propagates directly from the In to the On outputs. All outputs can be 3-stated by holding the OE pin at a logic HIGH. 74ALVC162839 Absolute Maximum Ratings Note 2 Supply Voltage VCC DC Input Voltage VI Output Voltage VO Note 3 DC Input Diode Current IIK VI < 0V DC Output Diode Current IOK VO < 0V DC Output Source/Sink Current IOH/IOL DC VCC or GND Current per Supply Pin ICC or GND Storage Temperature Range TSTG −0.5V to +4.6V −0.5V to 4.6V −0.5V to VCC +0.5V −50 mA −50 mA ±50 mA ±100 mA −65°C to +150°C Recommended Operating Conditions Note 4 Power Supply Operating 1.65V to 3.6V Input Voltage Output Voltage VO Free Air Operating Temperature TA Minimum Input Edge Rate 0V to VCC 0V to VCC −40°C to +85°C VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V Note 2 The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 3 IO Absolute Maximum Rating must be observed.

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74ALVC162839 Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs/Outputs and Series Resistors in the Outputs
74ALVC162839

Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs/Outputs and Series Resistors in the Outputs

The ALVC162839 contains twenty non-inverting selectable buffered or registered paths. The device can be configured to operate in a registered, or flow through buffer mode by utilizing the register enable REGE and Clock CLK signals. The device operates in a 20-bit word wide mode. All outputs can be placed into 3-STATE through use of the OE pin. These devices are ideally suited for buffered or registered 168 pin and 200 pin SDRAM DIMM memory modules.

The 74ALVC162839 is designed for low voltage 1.65V to 3.6V VCC applications with I/O compatibility up to 3.6V. The 74ALVC162839 is also designed with series resistors in the outputs. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters.

The 74ALVC162839 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
s Compatible with PC100 and PC133 DIMM module specifications
s VCC supply operation s 3.6V tolerant inputs and outputs s series resistors in the outputs s tPD CLK to On
ns max for 3.0V to 3.6V VCC ns max for 2.3V to 2.7V VCC ns max for 1.65V to 1.95V VCC s Power-off high impedance inputs and outputs s Supports live insertion and withdrawal Note 1 s Uses patented noise/EMI reduction circuitry s Latchup conforms to JEDEC JED78 s ESD performance Human body model > 2000V Machine model > 200V

Note 1 To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:

Order Number Package Number

Package Description
74ALVC162839T

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Pin Descriptions

Pin Names

OE CLK REGE

Description Output Enable Input Active LOW

Inputs Outputs Clock Input Register Enable Input
2001 Fairchild Semiconductor Corporation DS500712
74ALVC162839

Connection Diagram Logic Diagram

Truth Table

Inputs

Outputs

REGE

H = Logic HIGH L = Logic LOW X = Don’t Care, but not floating Z = High Impedance = LOW-to-HIGH Clock Transition

Functional Description

The 74ALVC162839 consists of twenty selectable noninverting buffers or registers with word wide modes. Mode functionality is selected through operation of the CLK and REGE pin as shown by the truth table. When REGE is held at a logic HIGH the device operates as a 20-bit register. Data is transferred from In to On the rising edge of the CLK input. When the REGE pin is held at a logic LOW the device operates in a flow through mode and data propagates directly from the In to the On outputs. All outputs can be 3-stated by holding the OE pin at a logic HIGH.
74ALVC162839

Absolute Maximum Ratings Note 2

Supply Voltage VCC DC Input Voltage VI Output Voltage VO Note 3 DC Input Diode Current IIK

VI < 0V DC Output Diode Current IOK

VO < 0V DC Output Source/Sink Current

IOH/IOL DC VCC or GND Current per

Supply Pin ICC or GND Storage Temperature Range TSTG
−0.5V to +4.6V −0.5V to 4.6V
−0.5V to VCC +0.5V
−50 mA
−50 mA
±50 mA
±100 mA −65°C to +150°C

Recommended Operating Conditions Note 4

Power Supply

Operating
1.65V to 3.6V

Input Voltage

Output Voltage VO Free Air Operating Temperature TA Minimum Input Edge Rate
0V to VCC 0V to VCC −40°C to +85°C

VIN = 0.8V to 2.0V, VCC = 3.0V
10 ns/V

Note 2 The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Note 3 IO Absolute Maximum Rating must be observed.

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Datasheet ID: 74ALVC162839TX 513233