DK-DEV-10AX115S3ES

DK-DEV-10AX115S3ES Datasheet

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DK-DEV-10AX115S3ES	DK-DEV-10AX115S3ES (pdf)

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Arria 10 FPGA Development Kit User Guide Subscribe Send Feedback UG-01170 101 Innovation Drive San Jose, CA 95134 TOC-2 Arria 10 FPGA Development Kit Contents General Recommended Operating 1-2 Handling the 1-3 Getting 2-1 Installing the Subscription Edition 2-1 Activating Your 2-1 Installing the Development Installing the USB-Blaster 2-3 Development Board 3-1 Applying Power to the 3-1 Default Switch and Jumper Board Test 4-1 Preparing the Running the Board Test Using the Board Test Using the Configure 4-4 The System Info The GPIO 4-7 The Flash 4-9 The XCVR 4-11 The PCIe The FMC A 4-17 The FMC B The DDR3 4-23 The DDR4 4-25 The Power 4-27 The Clock 4-29 Board Board MAX V CPLD System FPGA 5-15 Configuring the FPGA Using 5-15 Status 5-15 User Altera Corporation Arria 10 FPGA Development Kit TOC-3 User-Defined Push User-Defined DIP 5-17 User-Defined Character 5-18 5-19 SDI Video Input/Output 5-20 Clock On-Board Off-Board Clock Components and 5-25 PCI 10/100/1000 Ethernet HiLo External Memory 5-29 5-36 5-43 5-45 5-45 5-48 5-48 Board Power 5-51 Power Distribution Power 5-52 External Memory FMC Loopback 5-56 Additional CE EMI Conformity A-1 Altera Corporation Overview UG-01170 Subscribe Send Feedback The 10 GX FPGA development board provides a hardware platform for evaluating the performance and features of the Arria 10 GX device. Figure 1-1 Overview of the Development Board Features 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered 101 Innovation Drive, San Jose, CA 95134 Recommended Operating Conditions Figure 1-2 Arria 10 GX Block Diagram MicroUSB MAX II On-Board USB Blaster TM II & USB Interface JTAG Chain This section describes the Arria 10 GX FPGA development board’s external memory interface support and also their signal names, types, and connectivity relative to the Arria 10 GX FPGA. The HiLo connector supports plugins the following memory interfaces • DDR3 x72 included in the kit • DDR4 x72 included in the kit • RLDRAM3 x36 included in the kit • QDR IV x36 not included. Contact your local Altera sales representative for ordering and availability Table 5-18 HiLo EMI Pin Assignments, Schematic Signal Names Board Reference F1 Schematic Signal Name FPGA Pin Number MEM_ADDR_CMD0 M32 I/O Standard Board Components Send Feedback Altera Corporation 5-30 HiLo External Memory Interface Board Reference H1 F2 G2 H2 J2 K2 G3 J3 L3 E4 F4 G4 H4 J4 K4 M1 M2 N2 L4 P5 M5 P1 R4 M4 Schematic Signal Name FPGA Pin Number MEM_ADDR_CMD1 L32 MEM_ADDR_CMD2 N34 MEM_ADDR_CMD3 M35 MEM_ADDR_CMD4 L34 MEM_ADDR_CMD5 K34 MEM_ADDR_CMD6 M33 MEM_ADDR_CMD7 L33 MEM_ADDR_CMD8 J33 MEM_ADDR_CMD9 J32 MEM_ADDR_CMD10 H31 MEM_ADDR_CMD11 J31 MEM_ADDR_CMD12 H34 MEM_ADDR_CMD13 H33 MEM_ADDR_CMD14 G32 MEM_ADDR_CMD15 E32 MEM_ADDR_CMD16 F33 MEM_ADDR_CMD17 G35 MEM_ADDR_CMD18 H35 MEM_ADDR_CMD19 G33 MEM_ADDR_CMD20 U33 MEM_ADDR_CMD21 T33 MEM_ADDR_CMD22 R34 MEM_ADDR_CMD23 P34 MEM_ADDR_CMD24 N33 V 1.5V V I/O Standard UG-01170 Altera Corporation Board Components Send Feedback UG-01170 HiLo External Memory Interface 5-31 Board Reference Schematic Signal Name FPGA Pin Number I/O Standard MEM_ADDR_CMD25 P33 MEM_ADDR_CMD26 F32 MEM_ADDR_CMD27 T35 MEM_ADDR_CMD28 T34 MEM_ADDR_CMD29 E35 MEM_ADDR_CMD30 U32 MEM_ADDR_CMD31 T32 MEM_CLK_N MEM_CLK_P MEM_DMA0 MEM_DMA1 MEM_DMA2 MEM_DMA3 MEM_DMB0 AB32 MEM_DMB1 AG31 MEM_DMB2 MEM_DMB3

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Arria 10 FPGA Development Kit User Guide

Subscribe Send Feedback

UG-01170
101 Innovation Drive San Jose, CA 95134

TOC-2

Arria 10 FPGA Development Kit

Contents

General Recommended Operating 1-2 Handling the 1-3

Getting 2-1

Installing the Subscription Edition 2-1 Activating Your 2-1

Installing the Development Installing the USB-Blaster 2-3

Development Board 3-1

Applying Power to the 3-1 Default Switch and Jumper

Board Test 4-1

Preparing the Running the Board Test Using the Board Test

Using the Configure 4-4 The System Info The GPIO 4-7 The Flash 4-9 The XCVR 4-11 The PCIe The FMC A 4-17 The FMC B The DDR3 4-23 The DDR4 4-25 The Power 4-27 The Clock 4-29

Board

Board MAX V CPLD System FPGA 5-15

Configuring the FPGA Using 5-15 Status 5-15 User

Altera Corporation

Arria 10 FPGA Development Kit

TOC-3

User-Defined Push User-Defined DIP 5-17 User-Defined Character 5-18 5-19 SDI Video Input/Output 5-20 Clock On-Board Off-Board Clock Components and 5-25 PCI 10/100/1000 Ethernet HiLo External Memory 5-29 5-36 5-43 5-45 5-45 5-48 5-48 Board Power 5-51 Power Distribution Power 5-52 External Memory FMC Loopback 5-56

Additional

CE EMI Conformity A-1

Altera Corporation

Overview

UG-01170

Subscribe

Send Feedback

The 10 GX FPGA development board provides a hardware platform for evaluating the performance and features of the Arria 10 GX device.

Figure 1-1 Overview of the Development Board Features
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO 9001:2008 Registered
101 Innovation Drive, San Jose, CA 95134

Recommended Operating Conditions

Figure 1-2 Arria 10 GX Block Diagram

MicroUSB

MAX II

On-Board USB Blaster TM II & USB Interface

JTAG Chain
This section describes the Arria 10 GX FPGA development board’s external memory interface support and also their signal names, types, and connectivity relative to the Arria 10 GX FPGA. The HiLo connector supports plugins the following memory interfaces
• DDR3 x72 included in the kit
• DDR4 x72 included in the kit
• RLDRAM3 x36 included in the kit
• QDR IV x36 not included. Contact your local Altera sales representative for ordering and availability

Table 5-18 HiLo EMI Pin Assignments, Schematic Signal Names

Board Reference F1

Schematic Signal Name FPGA Pin Number MEM_ADDR_CMD0 M32

I/O Standard

Board Components Send Feedback

Altera Corporation
5-30

HiLo External Memory Interface

Board Reference H1 F2 G2 H2 J2 K2 G3 J3 L3 E4 F4 G4 H4 J4 K4 M1 M2 N2 L4 P5 M5 P1 R4 M4

Schematic Signal Name FPGA Pin Number MEM_ADDR_CMD1 L32 MEM_ADDR_CMD2 N34 MEM_ADDR_CMD3 M35 MEM_ADDR_CMD4 L34 MEM_ADDR_CMD5 K34 MEM_ADDR_CMD6 M33 MEM_ADDR_CMD7 L33 MEM_ADDR_CMD8 J33 MEM_ADDR_CMD9 J32 MEM_ADDR_CMD10 H31 MEM_ADDR_CMD11 J31 MEM_ADDR_CMD12 H34 MEM_ADDR_CMD13 H33 MEM_ADDR_CMD14 G32 MEM_ADDR_CMD15 E32 MEM_ADDR_CMD16 F33 MEM_ADDR_CMD17 G35 MEM_ADDR_CMD18 H35 MEM_ADDR_CMD19 G33 MEM_ADDR_CMD20 U33 MEM_ADDR_CMD21 T33 MEM_ADDR_CMD22 R34 MEM_ADDR_CMD23 P34 MEM_ADDR_CMD24 N33

V 1.5V V

I/O Standard

UG-01170

Altera Corporation

Board Components Send Feedback

UG-01170

HiLo External Memory Interface
5-31

Board Reference

Schematic Signal Name FPGA Pin Number

I/O Standard

MEM_ADDR_CMD25 P33

MEM_ADDR_CMD26 F32

MEM_ADDR_CMD27 T35

MEM_ADDR_CMD28 T34

MEM_ADDR_CMD29 E35

MEM_ADDR_CMD30 U32

MEM_ADDR_CMD31 T32

MEM_CLK_N

MEM_CLK_P

MEM_DMA0

MEM_DMA1

MEM_DMA2

MEM_DMA3

MEM_DMB0

AB32

MEM_DMB1

AG31

MEM_DMB2

MEM_DMB3

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived DK-DEV-10AX115S3ES Datasheet file may be downloaded here without warranties.

Datasheet ID: DK-DEV-10AX115S3ES 517129