EP1K30FC256-3AA

EP1K30FC256-3AA Datasheet

EP1K10

Part	Datasheet
EP1K30FC256-3AA	EP1K30FC256-3AA (pdf)

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PDF Datasheet Preview
May 2003, ver. ACEX 1K Programmable Logic Device Family Data Sheet Features... • Programmable logic devices PLDs , providing low cost system-on-a-programmable-chip SOPC integration in a single device Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions Dual-port capability with up to 16-bit width per embedded array block EAB Logic array for general logic functions • High density 10,000 to 100,000 typical gates see Table 1 Up to 49,152 RAM bits 4,096 bits per EAB, all of which can be used without reducing logic capacity • Cost-efficient programmable architecture for high-volume applications Cost-optimized process Low cost solution for high-performance communications applications • Extended temperature range Table ACEXTM 1K Device Features Typical gates Maximum system gates Logic elements LEs EABs Total RAM bits Maximum user I/O pins EP1K10 10,000 56,000 576 3 12,288 136 EP1K30 30,000 119,000 1,728 6 24,576 171 EP1K50 50,000 199,000 2,880 10 40,960 249 EP1K100 100,000 257,000 4,992 12 49,152 333 Tools Altera Corporation DS-ACEX-3.4 ACEX 1K Programmable Logic Device Family Data Sheet ...and More Features Built-in Joint Test Action Group JTAG boundary-scan test BST circuitry compliant with IEEE Std. available without consuming additional device logic. Operate with a 2.5-V internal supply voltage In-circuit reconfigurability ICR via external configuration devices, intelligent controller, or JTAG port ClockLockTM and ClockBoostTM options for reduced clock delay, clock skew, and clock multiplication Built-in, low-skew clock distribution trees 100% functional testing of all devices test vectors or scan chains are not required Pull-up on I/O pins before and during configuration • Flexible interconnect continuous routing structure for fast, predictable interconnect delays Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators automatically used by software tools and megafunctions Dedicated cascade chain that implements high-speed, high-fan-in logic functions automatically used by software tools and megafunctions Tri-state emulation that implements internal tri-state buses Up to six global clock signals and four global clear signals • Powerful I/O pins Individual tri-state output enable control for each pin Open-drain option on each I/O pin Programmable output slew-rate control to reduce switching noise Clamp to VCCIO user-selectable on a pin-by-pin basis Supports hot-socketing Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet

PDF Datasheet Preview

May 2003, ver.

ACEX 1K

Programmable Logic Device Family

Data Sheet

Features...
• Programmable logic devices PLDs , providing low cost system-on-a-programmable-chip SOPC integration in a single device Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions Dual-port capability with up to 16-bit width per embedded array block EAB Logic array for general logic functions
• High density 10,000 to 100,000 typical gates see Table 1 Up to 49,152 RAM bits 4,096 bits per EAB, all of which can be used without reducing logic capacity
• Cost-efficient programmable architecture for high-volume applications Cost-optimized process Low cost solution for high-performance communications applications
• Extended temperature range

Table ACEXTM 1K Device Features

Typical gates Maximum system gates Logic elements LEs EABs Total RAM bits Maximum user I/O pins

EP1K10
10,000 56,000
576 3
12,288 136

EP1K30
30,000 119,000
1,728 6
24,576 171

EP1K50
50,000 199,000
2,880 10
40,960 249

EP1K100
100,000 257,000
4,992 12
49,152 333

Tools

Altera Corporation

DS-ACEX-3.4

ACEX 1K Programmable Logic Device Family Data Sheet
...and More Features

Built-in Joint Test Action Group JTAG boundary-scan test BST circuitry compliant with IEEE Std. available without consuming additional device logic.

Operate with a 2.5-V internal supply voltage In-circuit reconfigurability ICR via external configuration
devices, intelligent controller, or JTAG port ClockLockTM and ClockBoostTM options for reduced clock delay,
clock skew, and clock multiplication Built-in, low-skew clock distribution trees 100% functional testing of all devices test vectors or scan chains
are not required Pull-up on I/O pins before and during configuration
• Flexible interconnect continuous routing structure for fast,
predictable interconnect delays Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators automatically used by software tools and megafunctions Dedicated cascade chain that implements high-speed, high-fan-in logic functions automatically used by software tools and megafunctions Tri-state emulation that implements internal tri-state buses Up to six global clock signals and four global clear signals
• Powerful I/O pins Individual tri-state output enable control for each pin Open-drain option on each I/O pin Programmable output slew-rate control to reduce switching noise Clamp to VCCIO user-selectable on a pin-by-pin basis Supports hot-socketing

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

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Datasheet ID: EP1K30FC256-3AA 517124