AS4C8M16S-6BIN

AS4C8M16S-6BIN Datasheet

AS4C8M16S

Part	Datasheet
AS4C8M16S-6BIN	AS4C8M16S-6BIN (pdf)

Related Parts	Information
AS4C8M16S-7BCNTR	AS4C8M16S-7BCNTR
AS4C8M16S-6BINTR	AS4C8M16S-6BINTR
AS4C8M16S-7BCN	AS4C8M16S-7BCN

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AS4C8M16S Confidential 128M - 8M x 16 bit Synchronous DRAM SDRAM x Fast access time from clock ns x Fast clock rate 166/143 MHz x Fully synchronous operation x Internal pipelined architecture x 2M word x 16-bit x 4-bank x Programmable Mode registers - CAS Latency 2, or 3 - Burst Length 1, 2, 4, 8, or full page - Burst Type Sequential or Interleaved - Burst stop function x Auto Refresh and Self Refresh x 4096 refresh cycles/64ms x CKE power down mode x Single +3.3V r 0.3V power supply x Interface LVTTL x Operating temperature range - Commercial 0 ~ 70°C - Industrial -40 ~ 85°C - Automotive A2 -40 ~ 105°C x 54-pin 400 mil plastic TSOP II package x 54-ball x 1.2mm max FBGA package All parts ROHS Compliant Overview The 128Mb SDRAM is a high-speed CMOS synchronous DRAM containing 128 Mbits. It is internally configured as 4 Banks of 2M word x 16 DRAM with a synchronous interface all signals are registered on the positive edge of the clock signal, CLK . Read and write accesses to the SDRAM are burst oriented accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The SDRAM provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications. Table Key Specifications AS4C16M16S tCK3 Clock Cycle time min. tAC3 Access time from CLK max. tRAS Row Active time min. tRC Row Cycle time min. -6/7 6/7 ns 42/42 ns 60/63 ns Table Ordering Information Frequency Package AS4C8M16S-7TCN AS4C8M16S-6TCN 143 MHz 166 MHz 54 pin TSOP II 54 pin TSOP II AS4C8M16S-6TIN 166 MHz 54 pin TSOP II AS4C8M16S-6BIN AS4C8M16S-7BCN AS4C8M16S-6TAN T indicates TSOP II package 166 MHz 143 MHz 166 MHz 54 ball TFBGA 54 ball TFBGA 54 pin TSOP II B indicates TFBGA package N indicates Pb free and Halogen free ROHS compliant parts C Commercial I Industrial A Automotive temperatures Confidential Figure Pin Assignment Top View VDDQ VSSQ VDDQ VSSQ LDQM CAS# RAS# A10/AP DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 VDDQ NC/RFU UDQM AS4C8M16S Figure Ball Assignment Top View A VSS DQ15 VSSQ VDDQ DQ0 VDD B DQ14 DQ13 VDDQ

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AS4C8M16S

Confidential
128M - 8M x 16 bit Synchronous DRAM SDRAM
x Fast access time from clock ns x Fast clock rate 166/143 MHz x Fully synchronous operation x Internal pipelined architecture x 2M word x 16-bit x 4-bank x Programmable Mode registers
- CAS Latency 2, or 3 - Burst Length 1, 2, 4, 8, or full page - Burst Type Sequential or Interleaved - Burst stop function x Auto Refresh and Self Refresh x 4096 refresh cycles/64ms x CKE power down mode x Single +3.3V r 0.3V power supply x Interface LVTTL x Operating temperature range - Commercial 0 ~ 70°C - Industrial -40 ~ 85°C - Automotive A2 -40 ~ 105°C x 54-pin 400 mil plastic TSOP II package x 54-ball x 1.2mm max FBGA package All parts ROHS Compliant

Overview

The 128Mb SDRAM is a high-speed CMOS synchronous DRAM containing 128 Mbits. It is internally configured as 4 Banks of 2M word x 16 DRAM with a synchronous interface all signals are registered on the positive edge of the clock signal, CLK . Read and write accesses to the SDRAM are burst oriented accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.

The SDRAM provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications.

Table Key Specifications AS4C16M16S
tCK3 Clock Cycle time min. tAC3 Access time from CLK max. tRAS Row Active time min. tRC Row Cycle time min.
-6/7 6/7 ns 42/42 ns 60/63 ns
Table Ordering Information

Frequency

Package

AS4C8M16S-7TCN AS4C8M16S-6TCN
143 MHz 166 MHz
54 pin TSOP II 54 pin TSOP II

AS4C8M16S-6TIN
166 MHz
54 pin TSOP II

AS4C8M16S-6BIN AS4C8M16S-7BCN AS4C8M16S-6TAN T indicates TSOP II package
166 MHz 143 MHz 166 MHz
54 ball TFBGA 54 ball TFBGA 54 pin TSOP II

B indicates TFBGA package

N indicates Pb free and Halogen free ROHS compliant parts C Commercial I Industrial A Automotive temperatures

Confidential

Figure Pin Assignment Top View

VDDQ

VSSQ

VDDQ

VSSQ

LDQM

CAS#

RAS#

A10/AP

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

VDDQ

NC/RFU

UDQM

AS4C8M16S

Figure Ball Assignment Top View

A VSS DQ15 VSSQ

VDDQ DQ0 VDD

B DQ14 DQ13 VDDQ

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Datasheet ID: AS4C8M16S-6BIN 516138