EPC9048

EPC9048 Datasheet

Development Board EPC9048 Quick Start Guide

Part	Datasheet
EPC9048	EPC9048 (pdf)

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Development Board EPC9048 Quick Start Guide Half Bridge with Gate Drive for EPC2034 QUICK START GUIDE Demonstration System EPC9048 The EPC9048 development boards are in a half bridge topology with onboard gate drives, featuring the EPC2034 field effect transistors FETs . The purpose of these development boards is to simplify the evaluation process of these eGaN FETs by including all the critical components on a single board that can be easily connected into any existing converter. The development board is 2” x and contains two eGaN FETs in a half bridge configuration using the Texas Instruments UCC27611 gate driver, supply and bypass capacitors. The board contains all critical components and layout for optimal switching performance. There are also various probe points to facilitate simple waveform measurement and efficiency calculation. A complete block diagram of the circuit is given in Figure For more information on the EPC2034 eGaN FET please refer to the data sheet available from EPC at The data sheet should be read in conjunction with this quick start guide. QUICK START PROCEDURE The development boards are easy to set up to evaluate the performance of the eGaN FET. Refer to Figure 2 for proper connect and measurement setup and follow the procedure below: With power off, connect the input power supply bus to +VIN J5, J6 and ground / return to J7, J8 . With power off, connect the switch node of the half bridge OUT J3, J4 to your circuit as required. With power off, connect the gate drive input to +VDD J1, Pin-1 and ground return to J1, Pin-2 . With power off, connect the input PWM control signal to PWM J2, Pin-1 and ground return to any of the remaining J2 pins. Turn on the gate drive supply make sure the supply is between 7 V and 12 V range. Table 1 Performance Summary TA = 25°C Parameter Conditions Gate Drive Input Supply Range Min Max Units VIN Bus Input Voltage Range VOUT Switch Node Output Voltage 140 V 160 V IOUT Switch Node Output Current 12* A VPWM PWM Logic Input Voltage Threshold Input ‘High’ Input ‘Low’ Minimum ‘High’ State VPWM rise and fall 100 Input Pulse Width time < 10ns Minimum ‘Low’ State VPWM rise and fall 100# Input Pulse Width time < 10ns *Assumes inductive load, maximum current depends on die temperature actual maximum current will be subject to switching frequency, bus voltage and thermal management. # Dependent on time needed to ‘refresh’ high side bootstrap supply voltage.

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Development Board EPC9048 Quick Start Guide

Half Bridge with Gate Drive for EPC2034

QUICK START GUIDE

Demonstration System EPC9048

The EPC9048 development boards are in a half bridge topology with onboard gate drives, featuring the EPC2034 field effect transistors FETs . The purpose of these development boards is to simplify the evaluation process of these eGaN FETs by including all the critical components on a single board that can be easily connected into any existing converter.

The development board is 2” x and contains two eGaN FETs in a half bridge configuration using the Texas Instruments UCC27611 gate driver, supply and bypass capacitors. The board contains all critical components and layout for optimal switching performance. There are also various probe points to facilitate simple waveform measurement and efficiency calculation. A complete block diagram of the circuit is given in Figure

For more information on the EPC2034 eGaN FET please refer to the data sheet available from EPC at The data sheet should be read in conjunction with this quick start guide.

QUICK START PROCEDURE

The development boards are easy to set up to evaluate the performance of the eGaN FET. Refer to Figure 2 for proper connect and measurement setup and follow the procedure below:

With power off, connect the input power supply bus to +VIN J5, J6 and ground / return to J7, J8 .

With power off, connect the switch node of the half bridge OUT J3, J4 to your circuit as required.

With power off, connect the gate drive input to +VDD J1, Pin-1 and ground return to J1, Pin-2 .

With power off, connect the input PWM control signal to PWM J2, Pin-1 and ground return to any of the remaining J2 pins.

Turn on the gate drive supply make sure the supply is between 7 V and 12 V range.

Table 1 Performance Summary TA = 25°C

Parameter

Conditions

Gate Drive Input

Supply Range

Min Max Units

VIN Bus Input Voltage Range

VOUT

Switch Node

Output Voltage
140 V 160 V

IOUT

Switch Node Output

Current
12* A

VPWM

PWM Logic Input

Voltage Threshold

Input ‘High’

Input ‘Low’

Minimum ‘High’ State VPWM rise and fall 100

Input Pulse Width
time < 10ns

Minimum ‘Low’ State VPWM rise and fall 100#

Input Pulse Width
time < 10ns
*Assumes inductive load, maximum current depends on die temperature actual maximum current will be subject to switching frequency, bus voltage and thermal management. # Dependent on time needed to ‘refresh’ high side bootstrap supply voltage.

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Datasheet ID: EPC9048 510922