MT48LC16M16A2TG-6A:GTR

MT48LC16M16A2TG-6A:GTR Datasheet

MT48LC64M4A2 16 Meg x 4 x 4 banks MT48LC32M8A2 8 Meg x 8 x 4 banks MT48LC16M16A2 4 Meg x 16 x 4 banks

Part	Datasheet
MT48LC16M16A2TG-6A:GTR	MT48LC16M16A2TG-6A:GTR (pdf)

Related Parts	Information
MT48LC16M16A2TG-6A IT:GTR	MT48LC16M16A2TG-6A IT:GTR

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256Mb x4, x8, x16 SDRAM Features SDR SDRAM MT48LC64M4A2 16 Meg x 4 x 4 banks MT48LC32M8A2 8 Meg x 8 x 4 banks MT48LC16M16A2 4 Meg x 16 x 4 banks • PC100- and PC133-compliant • Fully synchronous all signals registered on positive edge of system clock • Internal, pipelined operation column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths 1, 2, 4, 8, or full page • Auto precharge, includes concurrent auto precharge and auto refresh modes • Self refresh mode not available on AT devices • Auto refresh 64ms, 8192-cycle commercial and industrial 16ms, 8192-cycle automotive • LVTTL-compatible inputs and outputs • Single +3.3V ±0.3V power supply Table 1 Address Table Parameter 16 Meg 64 Meg x 4 32 Meg x 8 x 16 Configuration 16 Meg x 4 8 Meg x 8 x 4 Meg x 16 x 4 banks 4 banks x 4 banks Refresh count Row addressing 8K A[12:0] 8K A[12:0] 8K A[12:0] Bank addressing 4 BA[1:0] 4 BA[1:0] 4 BA[1:0] Column addressing 2K A[9:0], A11 1K A[9:0] 512 A[8:0] Table 2 Key Timing Parameters CL = CAS READ latency Speed Clock Grade Frequency Access Time Setup CL = 2 CL = 3 Time Hold Time 167 MHz 5.4ns 1.5ns 0.8ns 143 MHz 5.4ns 1.5ns 0.8ns 133 MHz 5.4ns 1.5ns 0.8ns 133 MHz 5.4ns 1.5ns 0.8ns 100 MHz 6ns 1.5ns 0.8ns Options Marking • Configurations 64 Meg x 4 16 Meg x 4 x 4 banks 64M4 The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address. Micron Technology, Inc. reserves the right to change products or specifications without notice. 1999 Micron Technology, Inc. All rights reserved. 256Mb x4, x8, x16 SDRAM Mode Register Table 20 Burst Definition Table Burst Length 2 4 8 Continuous Starting Column Address Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 n = location Cn, Cn + 1, Cn + 2, Cn + 3...Cn - 1, Cn... Not supported For full-page accesses y = 2,048 x4 y = 1,024 x8 y = 512 x16 . For BL = 2, A11 x4 x8 or x16 select the block-of-two burst A0 selects the starting column within the block. For BL = 4, A11 x4 x8 or x16 select the block-of-four burst; select the starting column within the block. For BL = 8, A11 x4 x8 or x16 select the block-of-eight burst; select the starting column within the block. For a full-page burst, the full row is selected and A11 x4 x8 or x16 select the starting column. Whenever a boundary of the block is reached within a given sequence above, the fol- lowing access wraps within the block. For BL = 1, A11 x4 x8 or x16 select the unique column to be accessed, and mode register bit M3 is ignored. Micron Technology, Inc. reserves the right to change products or specifications without notice. 1999 Micron Technology, Inc. All rights reserved. 256Mb x4, x8, x16 SDRAM Mode Register CAS Latency The CAS latency CL is the delay, in clock cycles, between the registration of a READ command and the availability of the output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQ start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data is valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQ start driving after T1 and the data is valid by T2. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Figure 20 CAS Latency Command READ NOP tLZ NOP tOH DOUT CL = 2 Command READ NOP tLZ tAC CL = 3

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256Mb x4, x8, x16 SDRAM Features

SDR SDRAM

MT48LC64M4A2 16 Meg x 4 x 4 banks MT48LC32M8A2 8 Meg x 8 x 4 banks MT48LC16M16A2 4 Meg x 16 x 4 banks
• PC100- and PC133-compliant
• Fully synchronous all signals registered on positive
edge of system clock
• Internal, pipelined operation column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge
and auto refresh modes
• Self refresh mode not available on AT devices
• Auto refresh
64ms, 8192-cycle commercial and industrial 16ms, 8192-cycle automotive
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply

Table 1 Address Table

Parameter
16 Meg 64 Meg x 4 32 Meg x 8 x 16

Configuration
16 Meg x 4 8 Meg x 8 x 4 Meg x 16 x 4 banks 4 banks x 4 banks

Refresh count

Row addressing 8K A[12:0] 8K A[12:0] 8K A[12:0]

Bank addressing 4 BA[1:0] 4 BA[1:0] 4 BA[1:0]

Column addressing
2K A[9:0], A11
1K A[9:0]
512 A[8:0]

Table 2 Key Timing Parameters

CL = CAS READ latency

Speed

Clock

Grade Frequency

Access Time Setup CL = 2 CL = 3 Time

Hold Time
167 MHz
5.4ns 1.5ns 0.8ns
143 MHz
5.4ns 1.5ns 0.8ns
133 MHz
5.4ns 1.5ns 0.8ns
133 MHz 5.4ns 1.5ns 0.8ns
100 MHz 6ns
1.5ns 0.8ns

Options

Marking
• Configurations
64 Meg x 4 16 Meg x 4 x 4 banks
64M4
The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 1999 Micron Technology, Inc. All rights reserved.
256Mb x4, x8, x16 SDRAM Mode Register

Table 20 Burst Definition Table

Burst Length 2 4 8

Continuous

Starting Column Address

Order of Accesses Within a Burst

Type = Sequential

Type = Interleaved
0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2
0-1-2-3 1-0-3-2-3-0-1 3-2-1-0
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
n = location

Cn, Cn + 1, Cn + 2, Cn + 3...Cn - 1, Cn...

Not supported

For full-page accesses y = 2,048 x4 y = 1,024 x8 y = 512 x16 . For BL = 2, A11 x4 x8 or x16 select the block-of-two burst A0
selects the starting column within the block. For BL = 4, A11 x4 x8 or x16 select the block-of-four burst;
select the starting column within the block. For BL = 8, A11 x4 x8 or x16 select the block-of-eight burst;
select the starting column within the block. For a full-page burst, the full row is selected and A11 x4 x8 or
x16 select the starting column. Whenever a boundary of the block is reached within a given sequence above, the fol-
lowing access wraps within the block. For BL = 1, A11 x4 x8 or x16 select the unique column to be
accessed, and mode register bit M3 is ignored.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 1999 Micron Technology, Inc. All rights reserved.
256Mb x4, x8, x16 SDRAM Mode Register

CAS Latency

The CAS latency CL is the delay, in clock cycles, between the registration of a READ command and the availability of the output data. The latency can be set to two or three clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQ start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data is valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQ start driving after T1 and the data is valid by T2.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Figure 20 CAS Latency

Command

READ

NOP tLZ

NOP tOH

DOUT

CL = 2

Command

READ

NOP tLZ
tAC CL = 3

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MT48LC16M16A2TG-6A:GTR Datasheet file may be downloaded here without warranties.

Datasheet ID: MT48LC16M16A2TG-6A:GTR 516149